Understanding CPU Structure and Function in Computer Organization and Architecture
Exploring the intricate details of CPU architecture, this content delves into the essential tasks of fetching, interpreting, processing, and writing data. It discusses the significance of registers, user-visible registers, general-purpose registers, and condition code registers in CPU operations. Additionally, it highlights the number of general-purpose registers, their size requirements, and the impact on memory references. The content provides valuable insights into designing efficient processor structures and the top-level memory hierarchy considerations.
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William Stallings Computer Organization and Architecture 8thEdition Chapter 12 Processor Structure and Function
CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data
Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy
User Visible Registers General Purpose Data Address Condition Codes
General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data Accumulator Addressing Segment
General Purpose Registers (2) Make them general purpose Increase flexibility and programmer options Increase instruction size & complexity Make them specialized Smaller (faster) instructions Less flexibility
How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and takes up processor real estate See also RISC
How big? Large enough to hold full address Large enough to hold full word Often possible to combine two data registers C programming double int a; long int a;
Condition Code Registers Sets of individual bits e.g. result of last operation was zero Can be read (implicitly) by programs e.g. Jump if zero Can not (usually) be set by programs
VonNeumann Architecture Control & Status Registers Program Counter Instruction Decoding Register Memory Address Register Memory Buffer Register Revision: what do these all do? Program Counter (PC) Holds address of next instruction to be fetched Memory Address Register (MAR) Connected to address bus Specifies address for read or write op Memory Buffer Register (MBR) Connected to data bus Holds data to write or last data read Instruction Register (IR) Holds last instruction fetched
Program Status Word A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor
Other Registers May have registers pointing to: Process control blocks (see O/S) Interrupt Vectors (see O/S) N.B. CPU design and operating system design are closely linked
Example Register Organizations: 8086 processor Case study Explain -8086 Architecture -Register organization
Instruction Cycle Revision Stallings Chapter 3
Indirect Cycle May require memory access to fetch operands Indirect addressing requires more memory accesses Can be thought of as additional instruction subcycle
Data Flow (Instruction Fetch) Depends on CPU design In general: Fetch PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1
Data Flow (Instruction Fetch Diagram) Fetch PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1
Data Flow (Data Fetch) IR is examined If indirect addressing, indirect cycle is performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR
Data Flow (Indirect Diagram) IR is examined If indirect addressing, indirect cycle is performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR
Data Flow (Execute) May take many forms Depends on instruction being executed May include Memory read/write Input/Output Register transfers ALU operations
Data Flow (Interrupt) Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched
Data Flow (Interrupt Diagram) Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched
Prefetch Fetch accessing main memory Execution usually does not access main memory Can fetch next instruction during execution of current instruction Called instruction prefetch
Improved Performance But not doubled: Fetch usually shorter than execution Prefetch more than one instruction? Any jump or branch means that prefetched instructions are not the required instructions Add more stages to improve performance
Pipelining Fetch instruction Decode instruction Calculate operands (i.e. EAs) Fetch operands Execute instructions Write result Overlap these operations
Timing Diagram for Instruction Pipeline Operation
The Effect of a Conditional Branch on Instruction Pipeline Operation
Six Stage Instruction Pipeline
Chapter 16 Control Unit Operation No HW problems on this chapter. It is important to understand this material on the architecture of computer control units, and microprogrammed control units.
Basic Elements of Processor ALU Registers Internal data paths External data paths Control Unit
Single Bus Organization of CPU All components of CPU connected to single internal bus Makes interconnection structure simple External bus is connected to CPU via MAR and MBR
Instruction Micro-Operations A computer executes a program of instructions (or instruction cycles) Each instruction cycle has a number to steps or phases: Fetch, Indirect (if specified), Execute, Interrupt (if requested) These can be seen as micro-operations Each step does a modest amount of work Atomic operation of CPU
Constituent Elements of its Program Execution Machine Instruction is executed by executing set of micro operations
Types of Micro-operation Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops
Control Signals Clock One micro-instruction (or set of parallel micro- instructions) per clock cycle Instruction register Op-code for current instruction Determines which micro-instructions are performed Flags State of CPU Results of previous operations From control bus Interrupts Acknowledgements
Control Signals - output Within CPU Cause data movement Activate specific functions Via control bus To memory To I/O modules
Fetch - 4 Control Registers Utilized Program Counter (PC) Holds address of next instruction to be fetched Memory Address Register (MAR) Connected to address bus Specifies address for read or write op Memory Buffer Register (MBR) Connected to data bus Holds data to write or last data read Instruction Register (IR) Holds last instruction fetched
Fetch Cycle Address of next instruction is in PC Address (MAR) is placed on address bus t1: MAR (PC) Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR t2: MBR (memory) PC incremented by 1 (in parallel with data fetch from memory) PC (PC) +1 Data (instruction) moved from MBR to IR t3: IR (MBR) MBR is now free for further data fetches
Fetch Cycle Fetch Cycle: t1: MAR (PC) t2: MBR (memory) PC (PC) +1 t3: IR (MBR)
Fetch Cycle Let Tx be the time unit of the clock. Then: t1: MAR (PC) t2: MBR (memory) PC (PC) +1 t3: IR (MBR) Is this equally correct? Why? t1: MAR (PC) t2: MBR (memory) t3: PC (PC) +1 IR (MBR)
Basic Rules for Clock Cycle Grouping Proper sequence must be followed MAR (PC) must precede MBR (memory) Conflicts must be avoided Must not read & write same register at same time MBR (memory) & IR (MBR) must not be in same cycle Also: PC (PC) +1 involves addition Use ALU ? May need additional micro-operations
Indirect Cycle Indirect Cycle: t1: MAR (IRaddress) t2: MBR (memory) t3: IRaddress (MBRaddress) IR is now in same state as if direct addressing had been used (What does this say about IR size?)
Interrupt Cycle Interrupt Cycle: t1: MBR t2: MAR PC t3: memory (MBR) This is a minimum. May be additional micro-ops to get addresses (PC) save-address routine-address N.B. saving context is done by interrupt handler routine, not micro- ops
