Switched-Capacitor Circuits in Data Converters: Fall 2014 by Professor Y. Chiu
Explore the concepts of switched-capacitor circuits in data converters through the teachings of Professor Y. Chiu during the Fall 2014 semester. Delve into topics such as continuous-time integrators, switched capacitors, discrete-time integrators, and shunt-type vs. series-type capacitors in a comprehensive manner. Visual aids and detailed explanations help elucidate the workings of these circuits and their applications. Gain insights into the design, implementation, and advantages of various circuit configurations using switched capacitors in this educational journey.
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Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Switched-Capacitor Circuits 1
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Continuous-Time Integrator t 1 C2 ( ) t =- ( ) d v v o in R C V V 1 2 - R1 Vi 1 1 s Vo ( ) ( ) s =- H s = o R C i 1 2 =R C 1 2 C2 Goal: Vi SC Vo Approach: emulating resistors with switched capacitors 2
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Concept of Switched Capacitor Non-overlapping two-phase clock C 2 2 R VA VB VA VB <i> 1 1 i 1 1 R q T C T ( ) ( ) i= V -V i = = V -V 2 A B A B T C C T C R =C so, =R C = C =T 2 eq eq,1 2 2 1 1 A switched capacitor is a discrete-time resistor RC time constant set by capacitor ratio C2/C1 (match considerably better than R and C) and clock period T (flexibility) 3
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Switched Capacitors Shunt-type Series-type 2-phase clock C 1 2 1 VA VB VA VB 1 2 1 2 1 2 2 C 2( 1) C 2 VA VB Stray-insensitive 1( 2) 1 Shunt- and series-type SCs are simple and cheap to implement Stray-insensitive SC requires 2 more switches, what s the advantage besides being more flexible (i.e., w/ or w/o the T/2 delay)? 4
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Discrete-Time Integrator (DTI) Shunt-type Series-type C2 C2 2 1 2 C1 1 Vi Vo Vi Vo C1 2-phase clock 1 2 1 2 1 2 What are the VTFs (z-domain) of these DTIs, assuming no parasitic capacitance is present? 5
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Shunt-Type DTI T 1 C2 (sample) 1 2 1 2 1 2 Vi Vo vi(t) C1 (n-1) (n) 0 t (n+1) 2 C2 (update) vo(t) (n+1) (n) Vi Vo 0 t C1 (n-1) Charge conservation law (ideal): Total charge on C1 and C2 during 1 2 transition must remain unchanged! 6
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Shunt-Type DTI 1 2 C2 C2 (sample) (update) Vi Vi Vo Vo C1 C1 ( ) ( ) ( ) ( ) ( ) Q = V n C -V n C Q =0 C -V n+1 C 1 i 1 o 2 2 1 o 2 ( ) ( ) ( ) ( ) ( ) Q = Q V n C -V n C =0 C -V n+1 C 1 2 i 1 o 2 1 o 2 ( ) ( ) ( ) V z C -V z C =-z V z C i 1 o 2 o 2 ( ) ( ) V z V z C C 1-z C C 1-z z z -1 -1/2 ( ) o H z = =- or - 1 1 -1 -1 i 2 2 7
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Series-Type DTI T 1 2 1 2 1 2 1 2 (sample/update) (reset C1) vi(t) (n-1) (n) 0 t C2 2 (n+1) C1 1 Vi vo(t) (n) Vo (n-1) 0 t (n+1) ( ) ( ) V z V z C C 1-z 1 ( ) o H z = =- 1 VTF: -1 i 2 8
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Stray Capacitance Shunt-type Series-type 2 C2 C2 1 2 1 A C1 Vi Vo Vi Vo C1 A C C =4 2 Strays derive from D/S diodes and wiring capacitance 1 Cu Cu Cu VTF is modified due to strays Cu Cu Strays at the summing node is of no significance (virtual ground) C1 C2 9
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Stray-Insensitive SC Integrator C2 2( 1) C1 2 A B Vi Vo 1( 2) 1 Non-inverting Inverting C 1 C z -1 VTF: VTF: ( ) ( ) H z =-C 1-z 1 H z =+C 1-z 1 -1 -1 2 2 Capacitors can be significantly sized down to save power/area Sizes are eventually limited by kT/C noise, mismatch, etc. 10
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 SC Amplifier 1 C2 C1 C C 1 ( ) VTF: H z =+ z -1 1 Vi Vo 2 2 Non-integrating, memoryless (less the delay) Used in many applications of parametric amplification 11
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 SC Applications 12
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 CT Filter R L RLC prototype Vi C Vo R2 R4 CA R CB Active-RC Tow-Thomas CT biquad R1 R R3 Vi Vo 13
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 SC DT Filter R2 R4 CA R CB Active-RC Tow-Thomas CT biquad R1 R R3 Vi Vo C2 1 C4 2 CA CB SC DT biquad C1 C3 2 2 1 2 2 Vi Vo 1 1 2 1 14
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Sigma-Delta ( ) Modulator CI CS 1 2 Vi Do 2 1 +VR -VR 1-b DAC DTI + 1-bit comparator + 1-bit DAC = first-order ADC 15
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Pipelined ADC 2 C1 1 Vi C2 1 -VR/4 Vo 1 VR/4 -VR 2 1.5-b DAC 0 VR SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC 16
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 SC Common-Mode Feedback + + Vo Vo R R A A R R - - Vo Vo Vcmc Vcmc VBias Vcm Vcm-VBias CM sense amp can be replaced by a floating voltage source since the gain through the main op-amp is high enough. 17
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 SC Common-Mode Feedback 2 1 Vcm + Vo C 0.2C 2 1 A VBias C 0.2C 2 1 - Vo Vcm Vcmc + Vo Vcm-VBias A Vcm-VBias 1 - Vo 2 Vcmc 18
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Noise in SC Circuits 19
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Noise of CT Integrator H1(f) C C 2 R VN1 R Vi Vo Vo 2 VN2 H2(f) V V 2 2 2 2 ( ) f ( ) ( ) f ( ) f V = H f df + H df +... 2 N1 f N2 f oN 1 2 Noise in CT circuits can be simulated with SPICE (.noise) 20
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Noise of SC Integrator C2 C1 1 2 Vi Vo 2 1 1 2 1 2 1 2 SC circuits are NOT noise-free! Switches and op-amps introduce noise. 21
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Sampling ( 1) Ideal Voltage Source 2 2 VN1 R1 C1 VN2 Vi R2 V V 2 2 2 ( ) ( ) f + ( ) f ( ) V 1 = H f df 2 N1 f N2 f N 1 0 2 1 = 4kTR +4kTR df ( ) 1 2 1+ j2 f R +R C 0 1 2 kT =C Noise is indistinguishable from signal after sampling The noise acquired by C1 will be amplified in 2 just like signal 22
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Integration ( 2) H34(f) C2 2 2 VN3 C1 VN4 R4 Vo R3 2 VN5 H5(f) V V 2 2 V 2 2 2 ( ) ( ) f + ( ) f ( ) f ( ) f ( ) f V 2 = H df + H df +... 2 N3 f N5 f N4 f N 34 5 2 C C ( ) ( ) V = V 1 +V 2 2 2 2 1 oN N N 2 No simulator can directly simulate the aggregated output noise! 23
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Sampling ( 1) Noise Cascaded Stages C2 C2' C1 C1' 2 1 1 2 2 Vi Vo 1 2 2 1 C2 2 2 2 2 VN3 C1 VN4 R4 VN1 R1 C1' VN2 R3 R2 2 VN5 Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise (noise filtering). But parasitic loop delay may introduce peaking in freq. response, resulting in more integrated noise (noise peaking). 24
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Sampled Noise Spectrum CT PSD 0 fs 2fs Alias DT PSD 0 fs/2 fs 3/2fs Total integrated noise power remains constant SNR remains constant 25
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Non-ideal Effects in SC Circuits 26
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Non-ideal Effects in SC Circuits Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap, accumulation-mode gate cap, etc.) PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage coefficients negligible for most applications) Gate caps are typically good for up to 8-10 bits Switches (MOS transistors) Nonzero on-resistance (voltage dependent) (Nonlinear) stray capacitance added (Cgs, Cgd, Cgb, Cdb, Csb) Switch-induced sampling errors (charge injection, clock feedthrough, junction leakage, drain-source leakage, and gate leakage) Operational amplifiers Offset Finite-gain effects (voltage dependent) Finite bandwidth and slew rate (measured by settling speed) 27
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Non-ideal Effects of Switches 28
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Nonzero On-Resistance C Ron PMOS VGS NMOS VTp VTn Vout CS CMOS 0 Vout VDD W L CS ( ) R = C V -V -V -1 on ox DD th out FET channel resistance (thus tracking bandwidth) depends on signal level Usually (RonCS)-1 (3-5) -3dB of closed-loop op-amp for settling purpose 29
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Clock Bootstrapping 1 2 CS VDD In Out M1 CMOS Bootstrapped NMOS Small on-resistance leads to large switches large parasitic caps and large clock buffers Clock bootstrapping keeps VGS of the switch constant constant on- resistance (body effect?) and less parasitics w/o the PMOS 30
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Simplified Clock Bootstrapper 1 2 VDD Pros Linearity Bandwidth Cons Device reliability Complexity In Out M1 VDD M2 2 2 2 C 1 1 Out M1 2 In VSS 31
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Switch-Induced Errors Zi Clock feedthrough Cgs Cgd Vout Charge injection Vin Qch CS Channel charge injection and clock feedthrough (on drain side) result in charge trapped on CS after switch is turned off. 32
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Clock Feedthrough and Charge Injection VDD Vin+Vth Zi Cgs Cgd Vout 0 Vin Qch CS Switch on Switch off Both phenomena sensitive to Zi, CS, and clock rise/fall time Offset, gain error, and nonlinearity introduced to the sampling Clock feedthrough can be simulated by SPICE, but charge injection cannot be simulated with lumped transistor models 33
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Clock Rise/Fall-Time Dependence VDD Vin+Vth Zi Cgs Cgd Vout 0 Vin Qch CS Switch on Switch off Clock feedthrough Charge injection ( ) C WL V 2 C +C -V -V C ox DD th in V =- gs V =- V Fast turn-off ( ) DD C +C gs S gs S C ( ) gs V =- V +V V =0 Slow turn-off in th C +C gs S 34
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Dummy Switch Vin Vout W L W 2L CS Difficult to achieve precise cancellation due to the nonlinear dependence of V on Zi, CS, and clock rise/fall time Sensitive to the phase alignment between and _ 35
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 CMOS Switch Same size for Vin Vout P and N FETs CS Very sensitive to phase alignment between and _ Subject to threshold mismatch between PMOS and NMOS Exact cancellation occurs only for one specific Vin (which one?) 36
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Differential Signaling Vip Vop M1 CSp Balanced diff. input Vin Von M2 CSn Signal-independent errors (offset) and even-order distortions cancelled Gain error and odd-order nonlinearities remain 37
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Switch Performance 2 2 1 L L = = = R On-resistance: ( ) W on WL V V V C Q ( ) V V V C ox DD th i ch ox DD th i L 1 Q = BW ch Bandwidth: 2 R C L C on S S Q 1 V ch Charge injection: 2 C S Q L C Q 2 V BW 1 2 C L 2 2 = ch S Performance FoM: S ch Technology scaling improves switch performance! 38
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Leakage in SC Circuits 1= high , 2= low Vo(t) C2 2 2 C1 Vx Vi Vo I3 I2 I1 1 1 1 2 1 2 A0 0 t VB I1 diode leakage (existing in the old days too) I2 sub-threshold drain-source leakage of summing-node switch I3 gate leakage (FN tunneling) of amplifier input transistors Leakage currents are highly temperature- and process-dependent; the lower limit of clock frequency is often determined by leakage 39
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 DS Leakage 0.13- m CMOS A0 = Gm Ro = 90dB Ro 2M Rleak 0.6V/3 A 0.2M A0 = Gm (Rleak//Ro) 70dB + 2 CS VDD + CS 1e 1 + M1 + + Vi Vo 2e - - Vi Vo 2e - M1 - 1 CS 1e VDD - CS 2 VDD = 1.2V M2 Ileak M3 M4 VDD In Out M1 Out M1 In VSS = 0V 40
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Gate Leakage ( ) ( ) GS I WL exp -t exp V ox GS Direct tunneling through the thin gate oxide Short-channel MOSFET behaves increasingly like BJT s Violates the high-impedance assumption of the summing node 41
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Switch Size Optimization To minimize switch-induced error voltages, small transistor size, slow turn-off, low source impedance should be used. For fast settling (high-speed design), large W/L should be used, and errors will be inevitably large as well. Guidelines Always use minimum channel length for switches as long as leakage allows. For a given speed, switch sizes can be optimized w/ simulation. Be aware of the limitations of simulators (SPICE etc.) using lumped device models. 42
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Non-ideal Effects of Op-Amps 43
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Non-ideal Effects of Op-Amps Offset Finite-gain effects (voltage dependent) Finite bandwidth and slew rate (measured by settling speed) 44
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Offset Voltage C2 ( ) ( ) ( ) C1 Q = V n C + V n -V C 1 2 1 i 1 o os 2 Vi Vo 2 1 ( ) ( ) Vos Q =-V C + V n+1 -V C 2 os 1 o os 2 C C ( ) ( ) V =0 V n+1 -V n = V 1 Vo(t) i o o os 2 C C 1-z z -1 ( ) ( ) V z = V z 1 o i -1 1 2 1 2 2 0 t Vi = 0 45
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Autozeroing 1 ( ) ( ) Q = V n -V C -V C 1 i os 1 os 2 C2 2 ( ) ( ) Q =-V C + V n -V C C1 1 1 2 os 1 o os 2 Vi Vo 2 Vos ( ) ( ) V z V z C C ( ) o H z = = 1 i 2 Also eliminates low-frequency noise, e.g., 1/f noise A.k.a. correlated double sampling (CDS) 46
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Chopper Stabilization 2 Vn A B Vi A1 A2 Vo fC 1 -1 Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, A low-noise chopper-stabilized differential switched-capacitor filtering technique, IEEE Journal of Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981. 47
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Chopper Stabilization |Vi|2 0 2 Vn fC f A B Vi A1 A2 Vo SN(f) fC 1 -1 0 fC f |VA|2 0 Also eliminates DC offset voltage of A1 fC f |VB|2 0 fC f 48
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Chopper-Stabilized Differential Op-Amp Vi+ Vo+ Vo- Vi- Integrators/amplifiers can be built using these op-amps Some oversampling is useful to facilitate the implementation 49
Data Converters EECT 7327 Switched-Capacitor Circuits Professor Y. Chiu Fall 2014 Ideal SC Amplifier 1 C2 C1 C 1 A =C 1 Vi CL Vo 2 X 2 Closed-loop gain is determined by the capacitor ratio by design But this is assuming X is an ideal summing node (the op-amp is ideal) 50
