Understanding SAR ADC: Concepts and Implementation
Explore the operation and implementation of Successive-Approximation Register (SAR) Analog-to-Digital Converters (ADC), including binary search, charge redistribution, sampling, and conversion phases. Learn about N-bit ADCs and non-overlapping clock signals in this comprehensive guide.
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SAR ADC Tao Chen
Successive-approximation Register (SAR) ADC Chapter 17 Figure 05 Read chapter 17.2 2
Example timing diagram At convert start , SHA grabs a sample and hold its value Set DAC MSB to 1 as test bit, rest bits set to 0, DAC output compared to sample held If comparator output = 1, keep test bit as 1, else set test bit = 0 If test bit is LSB, reset busy and signal end of conversion Else, move test bit to next lower bit, and set it to 1, generate DAC output At end of conversion, DAC input code sent out as ADC output code 4
Charge redistribution implementation Vt _ C/2 C/4 C/4 C + VREF GND Vin
Vin = 1.3 Vref = 5V Sampling Phase Vt _ C/2 C/4 C/4 C + VREF GND Vin ( ) 0 2 = Q V C in
Vin = 1.3V Vref = 5V Conversion Phase 0 Vt _ C/2 C/4 C/4 C + VREF GND Vin ( ( ) 0 2 ) t V = = Q V C in = = 1.3 V V V t in 0 2 Q C
Vin = 1.3 Vref = 5V Conversion Phase 1 Vt _ 0 C/2 C/4 C/4 C + VREF GND Vin V ref ( 0 ) 0 2 ) t V = + = 1.2 V V V = = Q V C + t in 2 in ( ) ( Q C V V C ref t
Vin = 1.3 Vref = 5V Conversion Phase 2 Vt _ 1 C/2 C/4 C/4 C + VREF GND Vin V ref = + = ( ) 0 2 ) t V 0.05 V V = ( C Q = V C + t in 4 in 3 C ( ) 0 Q V V ref t 2 2
Vin = 1.3 Vref = 5V Conversion Phase 3 Vt _ 0 C/2 C/4 C/4 C + VREF GND Vin 3 V ( ( ) 0 2 ) t V ref = + = 0.575 V V = 5 Q V C C t in in 8 3 C ( ) = + 0 Q V V ref t 4 4
For N-bit ADC V N + ref i = V V B t in i 2 = 1 i Conversion Phase 0 can be skipped Non-overlapping Clock
Segmented CDAC Cb 2L-1Cu 2M-1C0 2Cu 2C0 C0 Cu Cu Vin Vref SAR Logic & control 14
Design Consideration Comparator: high speed, high resolution Capacitor: matching & KT/C (area) Switch: sampling time & conversion time
Project R-string R2R Flash SAR Size R Size R R-string CDAC (size C) Segmentation Decoder Decoder Comparator Comparator Switch Switch Encoder SAR Logic Buffer Buffer Bubble rm Switch Clock/Timing Power 2 s Power ENOB = [ /conv-step] J FoM ENOB f Speed Area State-of-the-art ADCs http://web.stanford.edu/~murmann/adcsurvey.html
Simulation Data converter simulation is very slow! Histogram test, spectral test takes hours to days! Server load is high at the end of the semester! Server crashes very often !! Start your project earlier !!!
