ASICs - Status

This content discusses the current status of ASICs at the University of Heidelberg, focusing on the DCD pipeline and standard versions submitted in 2013. It highlights the ongoing tests on EMCM, potential improvements for future submissions, and specific issues relating to transistor mismatch and current sources. The content also delves into the performance evaluation of individual ADCs in Chip #1, covering aspects such as noise levels, linearity deviations, and gain characteristics.

• ASICs
• University of Heidelberg
• ADC Characterization
• Improvements
• Performance Evaluation

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1. ASICs - Status Ivan Peri University of Heidelberg Germany 1

2. DCD Status DCDB DCDBv4 pipeline and standard versions submitted in 2013 Single chip and the tests on EMCM are ongoing (see talk E. Prinker) The first results are good all circuits tested and work Similarly as in previous chips, we have several sensitive ADCs pro chip which are distinguished by small missing code regions and higher noise The problem can be related to transistor mismatch and a poor ROUT of current sources can be fixed on the next chip Irradiation of DCDBv4 (pipeline) is planned at KIT-Karlsruhe A few things in DCD can be improved we are planning a new DCD submission for November 2014 or February 2015 Improvements: Fix JTAG DIN sampling moment to rising CLK edge (to be conform with the standard) Enlarge several transistors in ADC (comparator) for better matching, improve the ROUT of the current sources Further changes will be determined from measurement results 2

3. Chip #1 Test all ADCs ADC Characterization INL of first ADC DNL of first ADC first ADC s Noise 150 0.8 100 ADU DNL [ADU] Noise [ADU] INL [ADU] 3 80 0.7 100 2.5 60 0.6 40 50 2 0.5 20 0.4 0 1.5 0 0.3 -20 -50 1 -40 0.2 0.5 -60 -100 0.1 -80 -6 -6 -6 -6 10 10 10 10 0 0 0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30 10 12 14 16 18 20 22 24 26 Gain of All ADCs Mean Noise of All ADCs Peak-to-Peak INL of All ADCs DNL of All ADCs 100 10 10 DNL [ADU] Noise [ADU] INL [ADU] Gain [nA/ADU] 1.4 90 9 9 80 1.2 8 8 70 7 7 1 60 6 6 0.8 50 5 5 40 0.6 4 4 30 3 3 0.4 20 2 2 0.2 10 1 1 0 0 0 0 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 Gain vs. ADC Position DNL vs. ADC Position Mean Noise vs. ADC Position Peak-to-Peak INL vs. ADC Position 16 80 16 2 16 10 16 10 DCDB physical ADC location DCDB physical ADC location DCDB physical ADC location DCDB physical ADC location 78 1.8 9 9 14 14 14 14 76 1.6 8 8 12 12 12 12 74 1.4 7 7 10 10 10 10 72 1.2 6 6 8 70 8 1 8 5 8 5 68 0.8 4 4 6 6 6 6 66 0.6 3 3 4 4 4 4 64 0.4 2 2 2 2 2 2 62 0.2 1 1 0 60 0 0 0 0 0 0 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R11L11R12L12R 13L13R 14L14R 15L15R 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R 11L11R12L12R 13L13R 14L14R 15L15R 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R11L11R12L12R 13L13R 14L14R 15L15R 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R 11L11R12L12R 13L13R 14L14R 15L15R 3

4. Chip #1 Test all ADCs ADC characteristics Noise of the first ADC Deviation from mean for every input ADC Characterization INL of first ADC DNL of first ADC first ADC s Noise DNL: code difference for two consecutive inputs (first ADC) 150 0.8 100 ADU DNL [ADU] Noise [ADU] INL [ADU] 3 80 0.7 100 2.5 60 0.6 40 50 2 0.5 20 0.4 0 1.5 0 0.3 -20 INL of the first ADC Deviation from linear fit for every input -50 1 -40 0.2 0.5 -60 -100 0.1 -80 -6 -6 -6 -6 10 10 10 10 0 0 0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30 10 12 14 16 18 20 22 24 26 Peak-to-Peak INL of All ADCs INL (peak to peak for all inputs) Gain of All ADCs Mean Noise of All ADCs DNL of All ADCs 100 10 10 DNL [ADU] Noise [ADU] INL [ADU] Average noise (LSB) Gain [nA/ADU] 1.4 Gain (nA/LSB) 90 9 9 80 1.2 8 8 7 DNL (peak to peak for all inputs) 70 7 1 60 6 6 0.8 50 5 5 40 0.6 4 4 30 3 3 0.4 20 2 2 0.2 10 1 1 0 0 0 0 All ADCs: 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 Mean Noise vs. ADC Position Noise vs. ADC position Peak-to-Peak INL vs. ADC Position INL vs. ADC position DNL vs. ADC Position DNL vs. ADC position Gain vs. ADC Position 16 80 16 2 16 10 16 10 DCDB physical ADC location DCDB physical ADC location DCDB physical ADC location DCDB physical ADC location 78 1.8 9 9 14 14 14 14 76 1.6 8 8 12 12 12 12 74 1.4 7 7 Gain vs. ADC position 10 10 10 10 72 1.2 6 6 8 70 8 1 8 5 8 5 68 0.8 4 4 6 6 6 6 66 0.6 3 3 4 4 4 4 64 0.4 2 2 2 2 2 2 62 0.2 1 1 0 60 0 0 0 0 0 0 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R11L11R12L12R 13L13R 14L14R 15L15R 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R 11L11R12L12R 13L13R 14L14R 15L15R 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R11L11R12L12R 13L13R 14L14R 15L15R 0L0R1L1R2L2R3L3R4L4R5L5R6L6R7L7R8L8R9L9R10L10R 11L11R12L12R 13L13R 14L14R 15L15R 4

5. Chip #1 Test all ADCs Several bad ADCs (out of 128 tested) Gain of All ADCs Mean Noise of All ADCs Peak-to-Peak INL of All ADCs DNL of All ADCs 100 10 10 DNL [ADU] Noise [ADU] INL [ADU] Gain [nA/ADU] 1.4 90 9 9 Bad ADCs 80 1.2 8 8 70 7 7 1 60 6 6 0.8 50 5 5 40 0.6 4 4 30 3 3 0.4 20 2 2 0.2 10 1 1 0 0 0 0 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 5

6. Chip #1 Test all ADCs Noise of a bad ADC: ~1.3LSB (145e @ gq 650pA/e) ADC gain 73nA/LSB (~112e @ gq 650pA/e) INL of a bad ADC: ~5.3LSB Noise floor: ~0.58LSB (64e @ gq 650pA/e) Gain of All ADCs Mean Noise of All ADCs Peak-to-Peak INL of All ADCs DNL of All ADCs 100 10 10 DNL [ADU] Noise [ADU] INL [ADU] Gain [nA/ADU] 1.4 90 9 9 80 1.2 8 8 70 7 7 1 3LSBs 60 6 6 0.8 50 5 5 40 0.6 4 4 336e 30 3 3 0.4 20 2 2 0.2 10 1 1 0 0 0 0 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 0 20 40 60 80 100 120 6

7. Chip #2 Test all ADCs Another chip: no bad ADCs probably due to more careful optimization of bias parameters Question, why are some ADCs hard to optimize? ADC gain 72nA/LSB (~110e @ gq 650pA/e) Noise: ~0.55LSB (60e @ gq 650pA/e) Gain of All ADCs Mean Noise of All ADCs Peak-to-Peak INL of All ADCs DNL of All ADCs 100 5 10 DNL [ADU] Noise [ADU] INL [ADU] Gain [nA/ADU] 1.4 90 4.5 9 80 1.2 4 8 70 3.5 7 1 220e 60 3 6 275e 0.8 50 2.5 5 40 0.6 2 4 30 1.5 3 0.4 20 1 2 0.2 10 0.5 1 0 0 0 0 0 20 40 60 80 100 0 20 40 60 80 100 0 20 40 60 80 100 0 20 40 60 80 100 7

8. ADC unit-cell The ADC-unit has two current-memory cells based on two U-I converters A and B Depending on the input current amplitude (too low or too high), a reference current (4 A per cell) will be added or subtracted The comparison is done in the following way: Two copies of the current stored in A are made this is done with the two, layout-identical, UI converters CL and CH that are connected to the same voltage as A The threshold currents are added 14u TooLow CL 12u+/-4u 10u TooHi A CH 12u+/-4u B 8

9. Unit-cell characteristics The purpose of the comparators is to assure that the reference currents are subtracted/added in the way so that the result current occupies two times smaller range Only so, we can multiply the output current by two IOut -8u -4u -2u IIn 8u 9

10. ADC unit-cell schematics In this figure, the transistor scheme of TooHi comparator is shown together with the bias currents Low PFB PFB 24u 24u RefFB 12u RefFB Sc1(5) Ith=10u Sc1(6) RefIn RefIn TooLow 24u 24u 24u 24u Sc2 Sc2 Sc2 Sc2 Original Copy 10

11. Offset Let us now assume that we have by 2 A higher current in the NMOS inside the copy U-I converter The relative current error is ~8.3% Low PFB PFB 24u 24u RefFB 12u RefFB Sc1(5) Ith=10u Sc1(6) RefIn RefIn TooLow 24u 24u 24u26u Sc2 Sc2 Sc2 Sc2 11

12. Unit-cell characteristics with offset The TooHigh-threshold is shifted IOut -8u -4u -2u IIn 8u 12

13. Bad characteristics causes missing codes This causes missing codes around 64 There are three other mismatch combinations CHI NMOS too weak (0) CLO NMOS too strong (0) CLO NMOS too weak (-64) They produce missing codes around indicated values IOut -8u -4u -2u IIn 8u 13

14. Origin of offset Why does the current offset happen? Possibility 1: transistor mismatch fix in the next chip: make the layout in a better way e.g. the transistors bigger Low PFB PFB 24u 24u RefFB RefFB RefIn RefIn TooLow 24u 24u 24u26u Sc2 Sc2 Sc2 Sc2 14

15. Origin of offset Possibility 2: poor current source output characteristics (low ROUT) Notice: two output nodes are not on perfectly same potential Original UI converter connected to amplifier input, copy UI converter to RefIn Fix in next chip: resize the current source to have better ROUT Low PFB PFB 24u 24u RefFB RefFB RefIn RefIn TooLow 24u 24u 24u26u Sc2 Sc2 Sc2 Sc2 15

16. Possible adjustments Adjustments in this chip 1. Adjust the RefIn carefully to match with the amplifier input potential 2. Reduce the Sc2 (NMOS current source-) setting 3. Increase Sc1 (threshold-) setting Low PFB PFB 24u 24u 3 RefFB 12u RefFB Sc1(5) Ith=10u Sc1(6) RefIn RefIn TooLow 24u 24u 24u26u Sc2 Sc2 Sc2 Sc2 1 2 16

17. SWITCHER Status SWITCHER Irradiation of latest SWITCHER has been done at KIT (dose 30 MRad) The chip works after the irradiation Bumping issue: bumping so far done in HD-lab, this works well for prototyping but is slow for production Bumping with the required pitch (150 m) is not offered by the vendor (AMS/IBM) Solution: Company Pactec can place underbump metallization (ENIG) and solder bumps on single dies (price < 66 Eur/chip + 7.3 kEUR ~ 16k EUR) Backup solution: ordering of wafers from AMS MPW runs and bumping at IZM (probably possible in 2015 still to be confirmed) SWITCHER submission planned in 2015 Improvements: faster clear driver Separated control of the termination resistance for serial input (should be always on) and for the other fast inputs 17

18. UBM EING technology Pactec technology (from L. Andricek talk on DEPFET Workshop in Seeon 2014) 18

19. Single chip bumping Pactec technology (from L. Andricek talk on DEPFET Workshop in Seeon 2014) 19

20. Backup slides 20

21. DCDBPip TIA ADC 200 m 5 mm 21

22. Pipelined vs. Cyclic ADC Algorithm: Copy here copy there Compare with threshold add reference Add two outputs (duplicate) Pipeline ADC Memory cell ADC1 ADC2 MSB cell LSB cells 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 Hi Lo - Cyclic ADC approach - Algorithm performed cyclically (ping pong wise) by two memory cell pairs - Two ADCs per channel - 200ns sampling rate/ADC - ADC clocked with 100MHz - Pipeline ADC approach - Algorithm performed as in production line by 8 memory cell pairs - One ADC per channel - 100ns sampling rate when clocked with 50MHz - Designed for 50 ns sampling rate 22