Understanding JESD204B Physical Layer (PHY) in High-Speed Serial Interfaces

The JESD204B training presentation delves into the Physical Layer (PHY) of high-speed serial interfaces, covering topics such as speed grades, compliance types, SERDES solutions for long channels, clocking information, differential link data transmission, and electrical requirements for drivers and receivers. The content discusses the definition, characteristics, and key considerations of the PHY in JESD204B links, emphasizing the importance of signal interfaces, synchronization, and device clocking for optimal performance.

• JESD204B
• Physical Layer
• PHY
• High-Speed Interfaces
• SERDES Solutions

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1. JESD204B Training The Physical Layer (PHY) 5/29/2014 1

2. Overview What is the Physical Layer (PHY)? Speed Grades and Compliance Types SERDES Interface Solutions for Long/Lossy Channels Device Clock, SYSREF and SYNC~ Interfaces PCB Layout Recommendations 2

3. What is the Physical Layer (PHY)? The Physical Layer refers to the serial data transmitter and receiver of the JESD204B link Point-to-point, unidirectional serial interface Definition includes electrical and timing characteristics This presentation also considers the other signal interfaces JESD204B Subclass 1 ADC Interfaces JESD204B Subclass 1 DAC Interfaces Logic Device Logic Device ADC DAC SERDES SERDES SYNC~ SYNC~ DEV. CLOCK DEV. CLOCK DEV. CLOCK DEV. CLOCK SYSREF SYSREF SYSREF SYSREF Clock Device Clock Device 3

4. What is the Physical Layer (PHY)? Transmit and receiver data over a high- speed serial differential link Clocking information is embedded at TX and recovered at RX (CDR) Optional pulse-shaping and equalization techniques reduce error rate across link Transmitter (TX) Serialization Receiver (RX) De-Serialization w/ Character Alignment Equalization (Optional) Pulse Shaping Pre-/De-emphasis (Optional) Clock/Data Recovery (CDR) Differential Input Receiver Differential Output Driver 4

5. Speed Grades and Compliance The JESD204B standard defines 3 speed grade variants Based on OIF Optical standards (OIF-CEI-02.0) Variants differ most importantly in data rate, eye mask, and BER Parameter LV-OIF-Sx15 LV-OIF-6G-SR LV-OIF-11G-SR Data Rates 312.5Mbps 3.125Gbps 312.5Mbps - 6.375Gbps 312.5Mbps 12.5Gbps Differential Output Voltage 500 1000 (mV) 400 750 (mV) 360 770 (mV) Output Rise or Fall Time (20% - 80% into 100 load) 50 (ps) 30 (ps) 24 (ps) Bit Error Rate (BER) 1e-12 1e-15 1e-15 Compliance refers to AC or DC coupling and impacts the electrical characteristics of the driver/receiver 5

6. PHY Electrical Requirements Zrdiff / 2 Zddiff / 2 + PHY defines the I/O electrical structure of the driver and receiver Ztt Ztt + R_Vdiff -- -- Vdiff -- -- + - + - Vtt T_Vcm Zrdiff / 2 Zddiff / 2 Recevier Model Transmitter Model Common Mode Voltage Range Signal Swing Range Impedance and Return Losses 6

7. PHY Eye/Timing Requirements TX and RX Eye Masks with amplitude, rise-time, and jitter requirements RX must recover signal after channel loss and inter-symbol interference (ISI) Receive Eye Mask Transmit Eye Mask Random Jitter Random jitter plus Deterministic Jitter (ISI) 7 Bit-Error Rate

8. Solutions for Long/Lossy Channels Channel dielectric loss degrades the signal integrity of the signal Reduces the vertical/horizontal Eye opening and edge rate due to loss and inter-symbol interference (ISI) ISI is a form of deterministic jitter JESD204B Acceptable Loss Profile 5in. FR4 channel @ 7.4Gb/s 20in. FR4 channel @ 7.4Gb/s 8

9. Solutions for Long/Lossy Channels Equalization can be used to pulse-shape at TX or pulse-correct RX High-pass profile of equalization counteracts low-pass loss profile of channel Pre-emphasis AMPLIFY HIGH frequencies to achieve high-pass profile De-emphasis ATTENUATE LOW frequencies to achieve high-pass profile May require broadband amplification to meet eye requirements at large de- emphasis 5 10 15 Loss profile for microstrip trace lengths over FR4 20 High-pass emphasis profile (blue) matches the inverse of the channel loss profile (pink) 9

10. Solutions for Long/Lossy Channels ADC16DX370 De-Emphasis Waveform @ 5 Gb/s at TX output Maximum De-emphasis De-emphasis disabled Waveform @ 7.4 Gb/s at output of 20-inch FR4 channel De-emphasis Optimized De-emphasis disabled 10

11. Solutions for Long/Lossy Channels ADC12J4000 Pre-Emphasis Waveform @ 7 Gb/s over 7 inches FR4 Pre-emphasis Optimized Pre-emphasis disabled 11

12. TI Devices SERDES Summary Device Max Max Bit Rate Min #Lane/Ch. (at full MSPS) Emphasis / Equalization? Conversion Rate 370 MSPS 250 MSPS 4000 MSPS ADC16DX370 ADS42JB69 ADC12J4000 (Preview) DAC38J84 7.4 Gb/s 3.125 Gb/s 8 Gb/s 1 2 8 TX De-emphasis Not needed TX Pre-Emphasis 2500 MSPS 12.5 Gb/s 0.25 RX Adaptive Equalizer 12

13. Device Clock and SYSREF Interfaces No strict definition for electrical characteristics LVDS, LVPECL are common solutions Device clock frequency may be equal to sampling rate or multiple Noise on device clock typically sets jitter performance of converter Attention required for DC-coupled common-mode compatibility of TX/RX Subclass 1 SYSREF must meet setup/hold relative to device clock Electrical characteristics recommended to be consistent between device clock and SYSREF Subclass 2: SYSREF not required 13

14. SYSREF Interface (Signal Types) Periodic SYSREF always ON with periodic edges Risk of interferer spurs near IF due to SYSREF Periodic Gapped-Periodic Gapped-Periodic Send periodic edges for a brief pulse of time No spurs One-Shot One-Shot Single SYSREF pulse and then leave in logic-low state No spurs SYSREF pulse period equal to integer multiple of multi-frame period Disabling and gating the SYSREF signal may be employed TI Information NDA Required

15. SYNC~ Interface No strict definition for electrical characteristics LVDS, LVPECL, CMOS are common solutions DC coupling mandatory Subclass 1 SYNC~ does not have strict timing Subclass 2 SYNC~ must meet setup/hold relative to device clock Timing requirements very difficult to meet for device clock rates > 250MHz 15

16. Differential Interfaces (Example circuits) AC-Coupled Serial Lane Interface 0.01uF 100 -diff 100 PCB Channel Serial Lane Transmitter Serial Lane Receiver Serial Lane Interface AC or DC Coupling 100 differential channel Routing signal integrity is MOST critical of all JESD204B interface signals DC-Coupled Serial Lane Interface 100 -diff 100 PCB Channel Serial Lane Transmitter Serial Lane Receiver AC-Coupled Device Clock / SYSREF Interface Receiver 0.1uF Device Clock / SYSREF Interface AC or DC Coupling AC coupling SYSREF requires provision for DC balancing at receiver 100 differential channel Match device clock and SYSREF interface to meet setup/hold requirement 100 -diff 50 50 PCB Channel Transmitter VIS = 0.5V 10k DC-Coupled Device Clock / SYSREF Interface VCMO = 1.2V Receiver R2 R1 100 -diff 50 50 PCB Channel Transmitter VIS = 0.5V 10k 4*R1*R2 + 200*R1 = 1002 R2 / (R1+R2) = 0.55 / VCMO IDC (Each Side)= VCMO / (R1+R2) VCMO = 1.2V: R1 = 32.3 , R2 = 27.3 , , IDC = 20.1mA 16

17. Differential Interfaces (Example Circuits) SYNC~ Interface DC Coupling only 100 differential channel Routing VERY critical for subclass 2 Routing is LEAST critical for subclass 1 SYNC~ Receiver 100 -diff SYNC~ Transmitter PCB Channel 17

18. Generating Device Clocks and SYSREF Example: LMK04828 Subclass 1 capable 7 Device CLK / SYSREF pairs Low Jitter clock source SYSREF Disable feature Delay options LVPECL, LVDS, HSDS outputs Supports Clock Distribution mode using external clock source 18

19. PHY Debug (Test Patterns) Test patterns can verify the PHY layer signal integrity Pattern Use Test PRBS7 /15 /23 /31 Long pattern performance Deterministic Jitter (ISI) Random Noise 01010101010 (D21.5) PRBS and D21.5 patterns available on all TI JESD204B devices Most FPGA giga-bit transceivers have built-in PRBS generators/detectors 19

20. PHY Debug (Built-In Tools) HSDC Pro Eye Tool uses built-in Altera features to view signal integrity 20