Troubleshooting Guide for UCC28780 Implementation - Proto2 Debug

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This troubleshooting guide provides detailed steps for diagnosing issues related to the Proto2 system using the UCC28780 implementation. It includes measurements, waveforms, and observations to help identify and address problems such as rapid Vdd discharge and lack of step transitions on Vhvg. The guide also mentions the use of external components like NV6117 and ISO7710FD in the system setup for testing. Various measurements and calculations are discussed, along with adjustments made to components like the transformer and PWM signals.


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  1. Proto2 Debug- troubleshooting following TI Document re: UCC28780 Implementation sch of pdf attached. SLUC664 rev C xl for this app also attached.

  2. PROTO2 DEBUG-TROUBLESHOOTING STEPS TROUBLE: 0 PWML Why does Vdd discharge fast & no step transition on Vhvg? - - - CALCULATIONS PER XL REV , DC INPUT No parts missing or broken Soldering ok, no parts backwards - - No short. Can apply HVBULK TO 380V for testing. - - - Vdd to 17.5 No shorts on VDD, SWS,HVG, REF, RUN BAS126 OK BECAUSE IT does change state - - - - - - No shorts on VDD, SWS,HVG, REF, RUN No pulse even at 180v vbulk -CS PULL UP TO REF PRODUCES .3V. Xmfr pri reduced to 400uH & then to 200 uH Turn ratio on AUX lowered to 28:4 from 28 : 3 REF does not go up to 5V and its duration =fall time of VDD - Circuit uses NV6117,. External PWM on PWML applied thru ISO7710FD will switch NV6117 lower and then upper verified before installing UCC28780 - Isol7710FDs are powered separately thru bias using SN6505 xmfr. System has 5.2V input supplied.

  3. SLUUBV6-AUG 2018 Eval kit measurement on start up VDD & HVG waveforms- low Vbulk applied Blue: Vdd Red: Vhvg Vdd fall slowly & Vhvg controlled down to 11V after vdd rises to 17.5v as expected 50ms per div

  4. PROTO2 measurement on start up VDD & HVG waveforms- low Vbulk applied Trouble: 0 PWML Vdd & Vhvg coinciding for same value? Blue: Vdd Red: Vhvg Identical to VDD Vdd falls rapidly at the same rate as Vhvg from 17.5V to 10 V PWML pule count =0 No RUN step to hi. 50ms per div

  5. PROTO2 measurement on start up VDD & HVG waveforms- low Vbulk applied Trouble: 0 PWML Blue: Vdd Red: Vref- does not go to 5v Vdd falls rapidly at the same rate as Vhvg from 17.5V to 10 V PWML pule count =0 No RUN step to hi. 50ms per div

  6. Layout screenshot Bottom side

  7. Layout screenshot Top side Rcs Vdd caps=20uF

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