Conducting a BLDC Gate Driver Schematic Review and Debug Process
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2
W
h
a
t
y
o
u
’
l
l
l
e
a
r
n
:
•
How to locate EVM hardware files to use for comparison with engineer’s BLDC
driver schematic
•
Understand important schematic recommendations and decisions pertinent to
the BLDC driver and the MOSFET power stage
•
H
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A
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a
•
Purpose
•
Example Application – DRV8353
•
Schematic Review – DRV8353
•
Conclusion
3
P
u
r
p
o
s
e
•
When designing schematics for a BLDC
gate driver, there are many recommended
components to use
–
“Recommended External Components”
(Feature Description)
•
System design considerations must be
taken into account to debug and tune
system, depending on stage of evaluation
–
Requires understanding of BLDC application
required
•
Additional resources exist to make engineer
schematics easier to create, review, and
debug
–
EVM design files
4
A
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E
V
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F
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s
•
Outputs (PDF)
–
S
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c
–
Assembly
–
PCB Layers
•
Design Files (Altium)
–
.
P
r
j
P
c
b
–
.PcbDoc
–
.SchDoc
5
Best to compare/design
using PDF schematic and
Altium layout
E
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S
p
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a
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s
:
–
Motor voltage = 48V
–
Maximum current (loaded) = 40A
–
Gate driver = DRV8353H
•
A
d
d
i
t
i
o
n
a
l
i
n
f
o
r
m
a
t
i
o
n
:
–
Engineer first time designing a BLDC
system
–
Working on first revision of the schematic
–
6 months to evaluate and develop final
project
–
Final version should be robust and well-
tuned
–
Small form factor for final revision
6
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M
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7
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8
3
5
3
R
H
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E
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8
S
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G
a
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d
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a
p
a
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o
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s
•
H
i
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s
t
p
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t
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p
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s
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b
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t
o
t
h
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d
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v
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e
•
Recommended capacitors for driver:
–
VM / PVDD bypass caps
–
Charge pump flying/storage caps
–
Regulator caps, i.e AVDD, DVDD, VGLS, VREF,
bootstrap, etc.
•
Make sure right values and voltage ratings are
chosen
•
Voltage derating must be taken into account
(more info next slide)
9
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s
10
•
Ceramic capacitors have poor DC voltage derating performance
•
When exposed to the rated voltage, the cap will experience half the rated capacitance
•
Smaller capacitor sizes will experience more derating
•
Choose capacitors rated for 1.5x to 2x the supply voltage
S
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G
a
t
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d
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i
v
e
r
d
i
g
i
t
a
l
I
/
O
s
•
Fast switching I/Os:
–
PWM signals (INHx, INLx)
–
SPI signals (SDI, SDO, SCLK, nSCS)
–
CSA outputs (SOx, we will discuss later)
•
Slow switching I/Os:
–
H/W pins, ENABLE, nFAULT, etc.
•
A
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s
–
Internal pullups/pulldowns (i.e. ENABLE)
–
4-level/7-level inputs (H/W pins)
–
Open-drain configurations - external pullups
required (i.e. nFAULT, SDO)
–
Push-pull drivers (SDO in some devices)
11
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H
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P
I
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a
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–
Allows for fault diagnosis and more control of gate driver settings
–
Typically used for early revisions of board evaluation and system design
–
O
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1
e
x
t
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p
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q
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d
(
S
D
O
p
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p
)
12
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P
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.
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•
H
/
W
i
n
t
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r
f
a
c
e
–
Replaces SPI pins with 4 fixed H/W settings
via resistors to DVDD/GND
–
More difficult to diagnose faults and less
control of gate driver settings
–
Typically used for late revisions of board
evaluation once settings are finalized
–
H
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13
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G
a
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r
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r
o
u
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p
u
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s
•
Smart Gate Drive
technology:
–
Integrates passive components inside the
driver
–
Allows for gate current configurability
–
Automatically includes strong and weak
pulldown currents for efficient performance
•
Sometimes engineers want to use a lower
gate drive current, add more charge at the
gate, or have a stronger pulldown current
in the off state
•
E
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c
a
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p
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a
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:
–
A
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A
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t
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s
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/
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P
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a
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M
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F
E
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s
Many important MOSFET parameters to consider
depending on the application:
15
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3
R
x
-
E
V
M
(x3)
*Switching FETs fast requires careful analysis of gate waveforms, i.e.
overshoot and undershoot. Therefore IDRIVE selection and series gate
resistors must also be considered in this calculation.
S
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P
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F
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s
Many important MOSFET parameters to consider
depending on the application:
16
D
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V
8
3
5
3
R
x
-
E
V
M
(x3)
*Switching FETs fast requires careful analysis of gate waveforms, i.e.
overshoot and undershoot. Therefore IDRIVE selection and series gate
resistors must also be considered in this calculation.
S
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P
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t
a
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M
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F
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T
s
Many important MOSFET parameters to consider
depending on the application:
17
D
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V
8
3
5
3
R
x
-
E
V
M
(x3)
*Switching FETs fast requires careful analysis of gate waveforms, i.e.
overshoot and undershoot. Therefore IDRIVE selection and series gate
resistors must also be considered in this calculation.
S
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P
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a
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e
M
O
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F
E
T
s
Many important MOSFET parameters to consider
depending on the application:
18
D
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V
8
3
5
3
R
x
-
E
V
M
(x3)
*Switching FETs fast requires careful analysis of gate waveforms, i.e.
overshoot and undershoot. Therefore IDRIVE selection and series gate
resistors must also be considered in this calculation.
S
c
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m
a
t
i
c
R
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v
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–
P
o
w
e
r
s
t
a
g
e
M
O
S
F
E
T
s
Many important MOSFET parameters to consider
depending on the application:
19
D
R
V
8
3
5
3
R
x
-
E
V
M
(x3)
*Switching FETs fast requires careful analysis of gate waveforms, i.e.
overshoot and undershoot. Therefore IDRIVE selection and series gate
resistors must also be considered in this calculation.
S
i
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g
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v
s
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p
a
r
a
l
l
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l
M
O
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F
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T
s
•
MOSFETs can be placed in parallel for more current capability, but require
special schematic and layout design requirements to switch correctly
–
One FET may turn on faster than the other due to process variation
–
F
o
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m
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:
D
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P
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F
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A
p
p
B
r
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f
•
R
e
c
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m
m
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t
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a
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o
f
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c
h
F
E
T
–
Equivalent gate resistance is equal to each gate resistance added in parallel
20
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F
E
T
m
o
n
i
t
o
r
i
n
g
•
V
DS
monitoring for the high-side and low-side
MOSFETs through drain and source pins:
–
V
D
R
A
I
N
:
c
o
n
n
e
c
t
t
o
d
r
a
i
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f
H
S
F
E
T
–
S
H
x
:
c
o
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n
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c
t
t
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w
i
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c
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o
d
e
b
e
t
w
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F
E
T
s
–
S
L
x
:
c
o
n
n
e
c
t
t
o
s
o
u
r
c
e
o
f
L
S
F
E
T
–
S
P
x
:
c
o
n
n
e
c
t
t
o
h
i
g
h
s
i
d
e
o
f
s
h
u
n
t
r
e
s
i
s
t
o
r
•
Net ties or 0-ohm resistors can be used to
connect the names of VM to VDRAIN and motor
phase output to SHx
–
Makes naming conventions easier for handoff
between schematic and layout
21
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3
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3
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x
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E
V
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(x3)
S
c
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a
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w
–
P
h
a
s
e
d
i
a
g
n
o
s
t
i
c
s
&
s
n
u
b
b
e
r
s
•
DNP components may be useful for “tuning”
purposes but are not required by design
•
Depending on evaluation, engineers may find the
following issues depending on application and
layout:
22
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R
x
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E
V
M
(x3)
S
c
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w
–
S
h
u
n
t
r
e
s
i
s
t
o
r
s
•
Shunt resistors need to be selected carefully
for:
–
Accuracy
–
Differential voltage in linear range of the CSA
–
Power rating
–
Low inductance
•
SPx must be connected to high side of shunt
•
SNx must be connected to low side of shunt
•
Optional filtering caps between SPx/SNx
23
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3
5
3
R
x
-
E
V
M
(x3)
D
O
N
O
T
C
O
N
N
E
C
T
S
N
x
d
i
r
e
c
t
l
y
t
o
g
r
o
u
n
d
!
T
h
i
s
w
i
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p
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c
k
u
p
g
r
o
u
n
d
n
o
i
s
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i
n
t
o
t
h
e
C
S
A
o
u
t
p
u
t
.
S
c
h
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m
a
t
i
c
R
e
v
i
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w
–
S
h
u
n
t
r
e
s
i
s
t
o
r
a
n
d
C
S
A
c
a
l
c
u
l
a
t
i
o
n
s
•
Equations to calculate shunt resistor and
GAIN values needed using specifications:
–
Shunt resistor power: 2W
–
Motor application: +/- 40A
–
VREF = 3.3V
•
C
a
l
c
u
l
a
t
i
n
g
V
O
:
•
C
a
l
c
u
l
a
t
i
n
g
R
S
H
U
N
T
:
•
C
a
l
c
u
l
a
t
i
n
g
G
A
I
N
r
e
q
u
i
r
e
d
:
24
More gain = more resolution, less range
S
c
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m
a
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R
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v
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w
–
S
h
u
n
t
r
e
s
i
s
t
o
r
a
n
d
C
S
A
c
a
l
c
u
l
a
t
i
o
n
s
•
Equations to calculate shunt resistor and
GAIN values needed using specifications:
–
Shunt resistor power: 2W
–
Motor application: +/- 40A
–
VREF = 3.3V
•
C
a
l
c
u
l
a
t
i
n
g
V
O
:
•
C
a
l
c
u
l
a
t
i
n
g
R
S
H
U
N
T
:
•
C
a
l
c
u
l
a
t
i
n
g
G
A
I
N
r
e
q
u
i
r
e
d
:
25
More gain = more resolution, less range
S
c
h
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m
a
t
i
c
R
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v
i
e
w
–
C
u
r
r
e
n
t
F
e
e
d
b
a
c
k
•
Recommend low-pass RC filter at CSA
output depending on:
–
Algorithm used
–
PCB coupling
–
ADC technology (S&H, sigma-delta, etc.)
26
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P
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a
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a
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d
b
a
c
k
27
•
Resistor divider +
capacitor used to scale
motor and bus voltages to
ADCs for calculating
BEMF
•
Ways to protect ADC-
level voltages:
–
Insert TVS diodes rated
for ADC reference
voltages
–
Choose resistor divider
values that account for
voltage transients (i.e max
transient < ADC reference
votlage)
V
S
E
N
x
C
a
l
c
u
l
a
t
i
o
n
(
b
e
t
w
e
e
n
0
V
-
3
.
3
V
)
S
c
h
e
m
a
t
i
c
R
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Recommended to use a common ground because it
can dissipate motor currents and is thermally
sufficient
•
May result in noise coupling between motor
switching and analog/digital signals
•
Best to utilize at least 1 entire layer for ground
•
Layout should minimize power stage from interfering
with analog/digital signals to avoid noise coupling
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Split ground can be used to separate power stage
(PGND) from analog/digital signals (AGND/DGND)
•
May result in more inductance and worse
thermal performance
•
Thermal pad should typically be connected to PGND
•
Grounds should be tied together through a low-
inductance component (large 0-ohm resistor, net-tie,
etc.)
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AGND
PGND
GND
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Supply bulk capacitance used to suppress
excessive current demands or dumps with
changes in voltages due to:
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Highest current required
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Power supply’s ability to source current
–
Motor startup, generation, and braking
–
Acceptable supply voltage ripple
•
More bulk capacitance is beneficial, but results
in higher cost and physical size
•
Can be estimated using:
(assuming all system energy comes from motor)
29
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•
Hardware design files can be found on the EVM’s product page, including schematic and
layout
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Schematics should not only be designed based on the “Recommend External
Components” and EVM schematics, but also based on:
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Capacitor voltage deratings
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Efficient MOSFET performance
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CSA specifications (if used)
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System debuggability and evaluation
•
Consult TI Reference Designs and App Notes for information on schematic design, layout
practices, and high-power system design
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System Design Considerations for High-Power Motor Driver Applications
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Best Practices for Board Layout of Motor Drivers
•
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Exploring how to effectively review and debug a Brushless-DC (BLDC) motor driver schematic, focusing on locating EVM hardware files, understanding schematic recommendations, detecting errors, and providing valuable feedback. The process involves utilizing available resources to create, review, and debug engineer schematics efficiently, with examples such as the DRV8353 gate driver. Design considerations, system tuning, and the importance of recommended components in BLDC gate driver design are also discussed.
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Presentation Transcript
How to Conduct a BLDC Gate Driver Schematic Review and Debug Aaron Barrera Texas Instruments | Brushless-DC Motor Drivers 1
How to conduct a BLDC gate driver schematic review What you ll learn: How to locate EVM hardware files to use for comparison with engineer s BLDC driver schematic Understand important schematic recommendations and decisions pertinent to the BLDC driver and the MOSFET power stage How to detect errors and provide valuable feedback when reviewing a engineer s BLDC driver schematic 2
Agenda Purpose Example Application DRV8353 Schematic Review DRV8353 Conclusion 3
Purpose When designing schematics for a BLDC gate driver, there are many recommended components to use Recommended External Components (Feature Description) System design considerations must be taken into account to debug and tune system, depending on stage of evaluation Requires understanding of BLDC application required Additional resources exist to make engineer schematics easier to create, review, and debug EVM design files 4
Available EVM Hardware Files Outputs (PDF) Schematic Assembly PCB Layers Design Files (Altium) .PrjPcb .PcbDoc .SchDoc Best to compare/design using PDF schematic and Altium layout 5
Example Application Specifications: Motor voltage = 48V Maximum current (loaded) = 40A Gate driver = DRV8353H Additional information: Engineer first time designing a BLDC system Working on first revision of the schematic 6 months to evaluate and develop final project Final version should be robust and well- tuned Small form factor for final revision 6
Schematic Review Gate driver capacitors Highest priority to place gate driver capacitors as close as possible to the device Recommended capacitors for driver: VM / PVDD bypass caps Charge pump flying/storage caps Regulator caps, i.e AVDD, DVDD, VGLS, VREF, bootstrap, etc. Make sure right values and voltage ratings are chosen Voltage derating must be taken into account (more info next slide) DRV8353Rx- EVM 9
Capacitor voltage deratings Ceramic capacitors have poor DC voltage derating performance When exposed to the rated voltage, the cap will experience half the rated capacitance Smaller capacitor sizes will experience more derating Choose capacitors rated for 1.5x to 2x the supply voltage 10
Schematic Review Gate driver digital I/Os DRV8353Rx-EVM Fast switching I/Os: PWM signals (INHx, INLx) SPI signals (SDI, SDO, SCLK, nSCS) CSA outputs (SOx, we will discuss later) Slow switching I/Os: H/W pins, ENABLE, nFAULT, etc. Always check datasheet for logic pin diagrams Internal pullups/pulldowns (i.e. ENABLE) 4-level/7-level inputs (H/W pins) Open-drain configurations - external pullups required (i.e. nFAULT, SDO) Push-pull drivers (SDO in some devices) 11
SPI vs. Hardware interface SPI Interface Allows for fault diagnosis and more control of gate driver settings Typically used for early revisions of board evaluation and system design Only 1 external component usually required (SDO pullup) DRV8353Rx-EVM 12
SPI vs. Hardware interface DRV8353Rx-EVM H/W interface Replaces SPI pins with 4 fixed H/W settings via resistors to DVDD/GND More difficult to diagnose faults and less control of gate driver settings Typically used for late revisions of board evaluation once settings are finalized Helpful to include footprints for as many settings to allow for system configurability in early design 13
Schematic Review Gate driver outputs Smart Gate Drive technology: Integrates passive components inside the driver Allows for gate current configurability Automatically includes strong and weak pulldown currents for efficient performance Sometimes engineers want to use a lower gate drive current, add more charge at the gate, or have a stronger pulldown current in the off state Engineers can optionally: Add gate series resistors Add a gate-to-source resistor/capacitor DRV8353Rx-EVM 14
Schematic Review Power stage MOSFETs Many important MOSFET parameters to consider depending on the application: DRV8353Rx-EVM MOSFET Parameter Importance Must be higher than maximum motor current in application ID (max) (continuous drain current) Determines conduction losses (PCON) PCON = IRMS2 * RDS,ON RDS,ON (MOSFET on-resistance) (x3) Determines VDS rise/fall times* QGD = IDRIVE * tSLEW QGD (gate-to-drain charge) Must be higher than motor voltage Factors into switching losses (PSW) PSW = * VDS(MAX) * IDS(MAX) * (tRISE + tFALL) * fSW VDS (max) (drain-to-source voltage) *Switching FETs fast requires careful analysis of gate waveforms, i.e. overshoot and undershoot. Therefore IDRIVE selection and series gate resistors must also be considered in this calculation. 15
Schematic Review Power stage MOSFETs Many important MOSFET parameters to consider depending on the application: DRV8353Rx-EVM MOSFET Parameter Importance Must be higher than maximum motor current in application ID (max) (continuous drain current) Determines conduction losses (PCON) PCON = IRMS2 * RDS,ON RDS,ON (MOSFET on-resistance) (x3) Determines VDS rise/fall times* QGD = IDRIVE * tSLEW QGD (gate-to-drain charge) Must be higher than motor voltage Factors into switching losses (PSW) PSW = * VDS(MAX) * IDS(MAX) * (tRISE + tFALL) * fSW VDS (max) (drain-to-source voltage) *Switching FETs fast requires careful analysis of gate waveforms, i.e. overshoot and undershoot. Therefore IDRIVE selection and series gate resistors must also be considered in this calculation. 16
Schematic Review Power stage MOSFETs Many important MOSFET parameters to consider depending on the application: DRV8353Rx-EVM MOSFET Parameter Importance Must be higher than maximum motor current in application ID (max) (continuous drain current) Determines conduction losses (PCON) PCON = IRMS2 * RDS,ON RDS,ON (MOSFET on-resistance) (x3) Determines VDS rise/fall times* QGD = IDRIVE * tSLEW QGD (gate-to-drain charge) Must be higher than motor voltage Factors into switching losses (PSW) PSW = * VDS(MAX) * IDS(MAX) * (tRISE + tFALL) * fSW VDS (max) (drain-to-source voltage) *Switching FETs fast requires careful analysis of gate waveforms, i.e. overshoot and undershoot. Therefore IDRIVE selection and series gate resistors must also be considered in this calculation. 17
Schematic Review Power stage MOSFETs Many important MOSFET parameters to consider depending on the application: DRV8353Rx-EVM MOSFET Parameter Importance Must be higher than maximum motor current in application ID (max) (continuous drain current) Determines conduction losses (PCON) PCON = IRMS2 * RDS,ON RDS,ON (MOSFET on-resistance) (x3) Determines VDS rise/fall times* QGD = IDRIVE * tSLEW QGD (gate-to-drain charge) Must be higher than motor voltage Factors into switching losses (PSW) PSW = * VDS(MAX) * IDS(MAX) * (tRISE + tFALL) * fSW VDS (max) (drain-to-source voltage) *Switching FETs fast requires careful analysis of gate waveforms, i.e. overshoot and undershoot. Therefore IDRIVE selection and series gate resistors must also be considered in this calculation. 18
Schematic Review Power stage MOSFETs Many important MOSFET parameters to consider depending on the application: DRV8353Rx-EVM MOSFET Parameter Importance Must be higher than maximum motor current in application ID (max) (continuous drain current) Determines conduction losses (PCON) PCON = IRMS2 * RDS,ON RDS,ON (MOSFET on-resistance) (x3) Determines VDS rise/fall times* QGD = IDRIVE * tSLEW QGD (gate-to-drain charge) Must be higher than motor voltage Factors into switching losses (PSW) PSW = * VDS(MAX) * IDS(MAX) * (tRISE + tFALL) * fSW VDS (max) (drain-to-source voltage) *Switching FETs fast requires careful analysis of gate waveforms, i.e. overshoot and undershoot. Therefore IDRIVE selection and series gate resistors must also be considered in this calculation. 19
Single vs. parallel MOSFETs MOSFETs can be placed in parallel for more current capability, but require special schematic and layout design requirements to switch correctly One FET may turn on faster than the other due to process variation For more information: Driving Parallel MOSFETs App Brief Recommended to add gate resistance at gate of each FET Equivalent gate resistance is equal to each gate resistance added in parallel 20
Schematic Review FET monitoring VDS monitoring for the high-side and low-side MOSFETs through drain and source pins: VDRAIN: connect to drain of HS FET SHx: connect to switch node between FETs SLx: connect to source of LS FET SPx: connect to high side of shunt resistor Net ties or 0-ohm resistors can be used to connect the names of VM to VDRAIN and motor phase output to SHx Makes naming conventions easier for handoff between schematic and layout DRV8353Rx-EVM (x3) 21
Schematic Review Phase diagnostics & snubbers DNP components may be useful for tuning purposes but are not required by design DRV8353Rx-EVM Depending on evaluation, engineers may find the following issues depending on application and layout: Issue Workaround Include local bulk capacitance from VDRAIN to GND Place close to HS drain Typical ~1uF, VM-rated (x3) Positive transients at VDRAIN Include bypass capacitance from VDRAIN to SLx/SPx Place close to LS source Typical 0.1uF-1uF, VM-rated Negative transients at SPx/SLx Implement RC snubber Place parallel with MOSFET Typically DNP in first revision Calculate values through this FAQ Ringing at switch node 22
Schematic Review Shunt resistors Shunt resistors need to be selected carefully for: Accuracy Differential voltage in linear range of the CSA Power rating Low inductance SPx must be connected to high side of shunt SNx must be connected to low side of shunt Optional filtering caps between SPx/SNx DRV8353Rx-EVM (x3) DO NOT CONNECT SNx directly to ground! This will pick up ground noise into the CSA output. 23
Schematic Review Shunt resistor and CSA calculations Equations to calculate shunt resistor and GAIN values needed using specifications: Shunt resistor power: 2W Motor application: +/- 40A VREF = 3.3V Calculating VO: Calculating RSHUNT: Calculating GAIN required: More gain = more resolution, less range 24
Schematic Review Shunt resistor and CSA calculations Equations to calculate shunt resistor and GAIN values needed using specifications: Shunt resistor power: 2W Motor application: +/- 40A VREF = 3.3V Calculating VO: Calculating RSHUNT: Calculating GAIN required: More gain = more resolution, less range 25
Schematic Review Current Feedback Recommend low-pass RC filter at CSA output depending on: Algorithm used PCB coupling ADC technology (S&H, sigma-delta, etc.) 26
Schematic Review Phase and bus voltage feedback Resistor divider + capacitor used to scale motor and bus voltages to ADCs for calculating BEMF Ways to protect ADC- level voltages: Insert TVS diodes rated for ADC reference voltages Choose resistor divider values that account for voltage transients (i.e max transient < ADC reference votlage) VSENx Calculation (between 0V - 3.3V) 9.76? ????? = 48 ( 383? + 9.76?) ????? = 1.193? 27
Schematic Review Grounding Split Ground Common Ground Split ground can be used to separate power stage (PGND) from analog/digital signals (AGND/DGND) May result in more inductance and worse thermal performance Recommended to use a common ground because it can dissipate motor currents and is thermally sufficient May result in noise coupling between motor switching and analog/digital signals Thermal pad should typically be connected to PGND Best to utilize at least 1 entire layer for ground Grounds should be tied together through a low- inductance component (large 0-ohm resistor, net-tie, etc.) Layout should minimize power stage from interfering with analog/digital signals to avoid noise coupling GND AGND PGND 28
Schematic Review Bulk capacitance Supply bulk capacitance used to suppress excessive current demands or dumps with changes in voltages due to: Highest current required Power supply s ability to source current Motor startup, generation, and braking Acceptable supply voltage ripple More bulk capacitance is beneficial, but results in higher cost and physical size Can be estimated using: 1 2??????2>1 2??2 (assuming all system energy comes from motor) 29
Conclusion Hardware design files can be found on the EVM s product page, including schematic and layout Schematics should not only be designed based on the Recommend External Components and EVM schematics, but also based on: Capacitor voltage deratings Efficient MOSFET performance CSA specifications (if used) System debuggability and evaluation Consult TI Reference Designs and App Notes for information on schematic design, layout practices, and high-power system design System Design Considerations for High-Power Motor Driver Applications Best Practices for Board Layout of Motor Drivers BLDC schematic reviews are systematic and replicative practice makes perfect! 30
