Entering Budget Journal Voucher in Banner 9.1
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An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips Haocong Luo Ismail Emir Y ksel A. Giray Ya l k Onur Mutlu Mohammad Sadrosadati Ataberk Olgun
Read Disturbance in DRAM (I) DRAM Chip CPU Main Memory (DRAM Module) 2
Read Disturbance in DRAM (III) Read disturbance in DRAM breaks memory isolation Prominent example: RowHammer DRAM Row 1 Row 1 Row 1 Victim Row open closed open open closed Aggressor Row Row 2 Row 2 Row 2 Row 2 Row 2 Row 2 Victim Row Row 3 Row 3 Row 3 Repeatedly opening (activating) and closinga DRAM row many times causes RowHammer bitflips in adjacent rows [Kim, ISCA 14] [Kim, ISCA 20] [Luo+, ISCA 23] 3
Read Disturbance in DRAM (II) Another read disturbance phenomenon: RowPress DRAM Row 1 Row 1 Row 1 Victim Row open closed open closed open Aggressor Row Aggressor Row Row 2 Row 2 Row 2 Row 2 Row 2 Row 2 Victim Row Row 3 Row 3 Row 3 Keeping a DRAM row open for a long time causes bitflips in adjacent rows These bitflips do NOT require many row activations [Luo+, ISCA 23] 4
Motivation RowHammer and RowPress have different error mechanisms What if we combine them? DRAM Row 1 Hammered Aggressor Row Row 2 Row 2 Row 3 Pressed Aggressor Row Row 4 Row 4 Row 5 5
Executive Summary Goal: Experimentally characterize combined read disturbance from both RowHammer and RowPress in real DRAM chips Experimental Study: 84 DDR4 DRAM chips from 3 major Mfrs. Key Results: 1. Combined pattern takes significantly less time to induce the first bitflip compared to the state-of-the-art RowPress pattern (up to 46.1% faster) 2. The initial bits that flip are different across RowHammer, RowPress, and the combined patterns Hypothesis: The read disturbance caused by RowPress from one of the two aggressor rows in a double-sided pattern is much more significant than the other 6
Outline 1. DRAM & Read Disturbance Background 2. Combined RowHammer/RowPress Pattern 3. DRAMTesting Methodology 4. Major Characterization Results 5. Conclusion & Future Work 7
Outline 1. DRAM & Read Disturbance Background 2. Combined RowHammer/RowPress Pattern 3. DRAMTesting Methodology 4. Major Characterization Results 5. Conclusion & Future Work 8
DRAM Organization Hierarchical organization of a DRAM chip DRAM Array Row 0 Bank Row 1 Row 2 Row 3 Row 4 DRAM Bank DRAM Chip 9
Basic DRAM Operation DRAM is accessed at row granularity - The memory controller sends an activate (ACT) command to open the row - To access another row in the same bank, the memory controller sends a precharge (PRE) command, which closes the currently opened row tAggON: The time the aggressor row stays open - Minimal tAggON is tRAS (36ns) tAggON Command ACT PRE Time 10
DRAM Read Disturbance RowHammer: Repeatedly opening (activating) and closing a DRAM row (aggressor row) many times Open RowHammer Aggressor Row Close 36ns, 47K activations to induce bitflips RowPress: Keep an aggressor row open for a long period of time Open RowPress Aggressor Row Close 7.8 s, only 5K activations to induce bitflips RowHammerand RowPress have different underlying mechanisms 11 [Luo+, ISCA 23]
Outline 1. DRAM & Read Disturbance Background 2. Combined RowHammer/RowPress Pattern 3. DRAMTesting Methodology 4. Major Characterization Results 5. Conclusion & Future Work 12
Patterns Tested (I) Baseline 1: Conventional Single-Sided RowHammer/RowPress Pattern DRAM Victim Row Row 1 Row 1 tAggON 36ns Row 2 Row 2 Aggressor Row Pressed/Hammered Row 3 Row 3 Victim Row 13
Patterns Tested (II) Baseline 2: Conventional Double-Sided RowHammer/RowPress Pattern DRAM Victim Row Row 1 Row 1 tAggON 36ns Aggressor Row Row 2 Row 2 Pressed/Hammered Row 3 Row 3 Victim Row tAggON 36ns Aggressor Row Row 4 Row 4 Pressed/Hammered Victim Row Row 5 Row 5 14
Patterns Tested (III) Combined RowHammer and RowPress Pattern DRAM Victim Row Row 1 Row 1 Hammered tAggON1 = 36ns Aggressor Row Row 2 Row 2 Row 3 Row 3 Victim Row Pressed tAggON2 36ns Aggressor Row Row 4 Row 4 Victim Row Row 5 Row 5 15
Outline 1. DRAM & Read Disturbance Background 2. Combined RowHammer/RowPress Pattern 3. DRAMTesting Methodology 4. Major Characterization Results 5. Conclusion & Future Work 16
DRAM Testing Infrastructure DRAM Bender Testing Infrastructure Fine-grained control over DRAM commands and timings (1.5ns granularity) https://github.com/CMU-SAFARI/DRAM-Bender Olgun et al., "DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips," in TCAD, 2023. 17
Key Metrics 1. Time to First Bitflip: Time to induce at least one bitflip Lower is worse 2. ACmin: Total aggressor row activation count to induce at least one bitflip Lower is worse 18
Testing Methodology 84 Chips For each module - Evaluate the test patterns on 3K DRAM rows in a bank - Checkerboard data pattern (0xAA in the aggressor row and 0x55 in the victim row) - Repeat each experiment three times 19
Outline 1. DRAM & Read Disturbance Background 2. Combined RowHammer/RowPress Pattern 3. DRAMTesting Methodology 4. Major Characterization Results 5. Conclusion & Future Work 20
Major Characterization Results 1. Time to First Bitflip 2. ACmin 3. Bitflip Direction 4. Overlap between combined RH/RP bitflips and conventional RH and RP bitflips 21
Time to First Bitflip (I) 9x tREFI RowHammer tREFI std. dev. Aggressor Row On Time (tAggON) 22
Time to First Bitflip (II) 9x tREFI RowHammer tREFI std. dev. Aggressor Row On Time (tAggON) 23
Time to First Bitflip (III) 9x tREFI RowHammer tREFI std. dev. Aggressor Row On Time (tAggON) 24
Time to First Bitflip (IV) 78.9% Faster 37.6% Faster Aggressor Row On Time (tAggON) 25
Time to First Bitflip (V) Read disturbance bitflips can be induced in a smaller amount of time by combining RowPress and RowHammer compared to using solely RowPress 26
Major Characterization Results 1. Time to First Bitflip 2. ACmin 3. Bitflip Direction 4. Overlap between combined RH/RP bitflips and conventional RH and RP bitflips 27
ACmin (I) 40.5% fewer activations 48.0% fewer activations Aggressor Row On Time (tAggON) 28
ACmin (II) As tAggON initially starts to increase, combined pattern needs slightly more aggressor row activations to induce at least one bitflip than conventional double-sided RowPress pattern 29
Time to First Bitflip and ACmin Read disturbance bitflips can be induced in a smaller amount of time by combining RowPress and RowHammer compared to using solely RowPress As tAggON initially starts to increase, combined pattern needs slightly more aggressor row activations to induce at least one bitflip than conventional double-sided RowPress pattern Hypothesis As tAggON initially starts to increase, the read disturbance effect caused by RowPress from one of the two aggressor rows in double-sided pattern is much more significant than the other 30
Major Characterization Results 1. Time to First Bitflip 2. ACmin 3. Bitflip Direction 4. Overlap between combined RH/RP bitflips and conventional RH and RP bitflips 31
Bitflip Direction (I) As tAggON increases, the directionality of bitflips caused by combined RowHammer and RowPress pattern changes 32
Bitflip Direction (II) Hypothesis For large tAggON values, the read disturbance effect from RowPress is dominant compared to RowHammer in the combined RowHammer and RowPress pattern 33
Major Characterization Results 1. Time to First Bitflip 2. ACmin 3. Bitflip Direction 4. Overlap between combined RH/RP bitflips and conventional RH and RP bitflips 34
Overlap with Conventional RH and RP Overlap = ???????? ?????? ?? ???? ???????? ??? ???????????? ???????? ???????? ?????? ?? ???????? ??????? Bitflips caused by both combined and Bitflips caused by combined pattern Bitflips caused by conventional patterns conventional patterns 35
Overlap with Conventional RH and RP Overlap = ???????? ?????? ?? ???? ???????? ??? ???????????? ???????? ???????? ?????? ?? ???????? ??????? 36
Overlap with Conventional RH and RP Overlap = ???????? ?????? ?? ???? ???????? ??? ???????????? ???????? ???????? ?????? ?? ???????? ??????? Combined RowHammer and RowPress pattern induces different bitflips compared to the conventional single- and double-sided RowPress patterns 37
Outline 1. DRAM & Read Disturbance Background 2. Combined RowHammer/RowPress Pattern 3. DRAMTesting Methodology 4. Major Characterization Results 5. Conclusion & Future Work 38
Conclusion We experimentally characterize and demonstrate combined read disturbance from both RowHammer and RowPress in real DRAM chips Experimental Study: 84 DDR4 DRAM chips from all 3 major Mfrs. Key Results: 1. Combined pattern takes significantly less time to induce the first bitflip compared to the state-of-the-art RowPress pattern (up to 46.1% faster) 2. Initial bits that flip are different across RowHammer, RowPress, and combined patterns Hypothesis: The read disturbance caused by RowPress from one of the two aggressor rows in a double-sided pattern is much more significant than the other 39
Future Work Test more DRAM chips with more data patterns and temperatures (including possible aging effects) Examine the device-level mechanisms of RowHammer and RowPress to verify our hypotheses Understand the architectural implications by analyzing and evaluating how existing mitigation mechanisms need to be changed Lower overhead mitigations combining RH and RP, taking into account worst-case patterns 40
An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips Haocong Luo Ismail Emir Y ksel A. Giray Ya l k Onur Mutlu Mohammad Sadrosadati Ataberk Olgun arXiv version: https://arxiv.org/abs/2406.13080
Overlap with Conventional RH and RP Overlap = ?????? ?? ????? ?????????? ?? ???? ??? ???????? ??? ???????????? ???????? ?????? ?? ????? ?????????? ?? ??? ???????? ??????? 44
6F2 DRAM Cell Layout 45 https://m.blog.naver.com/leeneer/222749430430?view=img_3
Time to First Bitflip and ACmin (I) RowHammer std. dev. tREFI 9x tREFI Aggressor Row On Time (tAggON) 46
Time to First Bitflip (I) RowHammer std. dev. tREFI 9x tREFI Aggressor Row On Time (tAggON) 47
Time to First Bitflip (II) RowHammer std. dev. tREFI 9x tREFI Aggressor Row On Time (tAggON) 48
Time to First Bitflip and ACmin (I) RowHammer std. dev. tREFI 9x tREFI Aggressor Row On Time (tAggON) 49