Power System Dynamics and Stability: Exciters and Block Diagrams Overview
Explore the concepts of exciters and block diagrams in power system dynamics and stability through lectures by Prof. Tom Overbye at the University of Illinois. Learn about IEEE exciter models, including the evolution from T1 to DC1A, and delve into block diagram basics for simulating power system models. Stay updated on homework deadlines and exam details while enhancing your understanding of power system dynamics.
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ECE 576 Power System Dynamics and Stability Lecture 13: Exciters, Block Diagrams Prof. Tom Overbye Dept. of Electrical and Computer Engineering University of Illinois at Urbana-Champaign overbye@illinois.edu 1
Announcements Homework 4 is on the website and is due March 6 Read Chapter 4 Midterm exam is on March 13 in class Closed book, closed notes You may bring one 8.5 by 11" note sheet You do not have to write down model block diagram or the synchronous machine differential equations I'll supply those if needed Simple calculators allowed 2
IEEE T1 Exciter This model was standardized in the 1968 IEEE Committee Paper with Fig 1 shown below 3
IEEE T1 Evolution This model has been subsequently modified over the years, called the DC1 in a 1981 IEEE paper (modeled as the EXDC1 in stability packages) Note, KE in the feedback is the same as the 1968 approach Image Source: Fig 3 of "Excitation System Models for Power Stability Studies," IEEE Trans. Power App. and Syst., vol. PAS-100, pp. 494-509, February 1981 4
IEEE T1 Evolution In 1992 IEEE Std 421.5-1992 slightly modified it, calling it the DC1A (modeled as ESDC1A) VUEL is a signal from an under- excitation limiter, which we'll cover later Same model is in 421.5-2005 Image Source: Fig 3 of IEEE Std 421.5-1992 5
Initialization and Coding: Block Diagram Basics To simulate a model represented as a block diagram, the equations need to be represented as a set of first order differential equations Also the initial state variable and reference values need to be determined Next several slides quickly cover the standard block diagram elements 6
Integrator Block K I y u s Equation for an integrator with u as an input and y as an output is dy dt= K u I In steady-state with an initial output of y0, the initial state is y0 and the initial input is zero 7
First Order Lag Block K + Input u y Output of Lag Block 1 Ts Equation with u as an input and y as an output is dy 1 Ku y dt T ( ) = In steady-state with an initial output of y0, the initial state is y0 and the initial input is y0/K Commonly used for measurement delay (e.g., TR block with IEEE T1) 8
Derivative Block K s 1 sT + D y u D Block takes the derivative of the input, with scaling KD and a first order lag with TD Physically we can't take the derivative without some lag In steady-state the output of the block is zero State equations require a more general approach 9
State Equations for More Complicated Functions There is not a unique way of obtaining state equations for more complicated functions with a general form m du dt dy dt d u dt d dt + + + = u 0 1 m m n 1 n y d y dt + + + + y n 1 0 1 n 1 n To be physically realizable we need n >= m 10
General Block Diagram Approach One integration approach is illustrated in the below block diagram Image source: W.L. Brogan, Modern Control Theory, Prentice Hall, 1991, Figure 3.7 11
Derivative Example Write in form K s D T D + 1 T s D Hence 0=0, 1=KD/TD, 0=1/TD Define single state variable x, then dx dt y Initial value of x is found by recognizing y is zero so x = - 1u = = u y 0 0 T D K T = + = + y x u x u D 1 D 12
Lead-Lag Block + 1 sT 1 sT + input A y u Output of Lead/Lag B In exciters such as the EXDC1 the lead-lag block is used to model time constants inherent in the exciter; the values are often zero (or equivalently equal) In steady-state the input is equal to the output To get equations write in form with 0=1/TB, 1=TA/TB, 0=1/TB T T 1 + s A + 1 sT 1 sT + T 1 T = A B B s + B B 13
Lead-Lag Block The equations are with 0=1/TB, 1=TA/TB, 0=1/TB then dx dt 1 The steady-state requirement that u = y is readily apparent ( ) = = u y u y 0 0 T T T B = + = + y x u x u A 1 B 14
Limits: Windup versus Nonwindup When there is integration, how limits are enforced can have a major impact on simulation results Two major flavors: windup and non-windup Windup limit for an integrator block Lmax v The value of v is NOT limited, so its value can "windup" beyond the limits, delaying backing off of the limit K I u y s Lmin If Lmin v Lmax then y = v else If v < Lmin then y = Lmin, else if v > Lmax then y = Lmax dv dt= K u I 15
Non-Windup Limits Integrator Block With non-windup limits, the value of the integral (v previously) is prevented from exceeding its limit. Thus it can immediately back off its limits dy dt= Lmax K u K I I u y (except as indicated below) s dy dt Lmin = If L y L then normal K u min max I dy dt dy dt = If y L then y=L and if > 0 then u 0 max max = If y L then y=L and if < 0 then u 0 min min 16
Limits on First Order Lag Windup and non-windup limits are handled in a similar manner for a first order lag dv dt 1Ku T = ( ) v Lmax K + v If Lmin v Lmax then y = v else If v < Lmin then y = Lmin, else if v > Lmax then y = Lmax u y 1 sT Lmin Again the value of v is NOT limited, so its value can "windup" beyond the limits, delaying backing off of the limit 17
Non-Windup Limit First Order Lag With a non-windup limit, the value of y is prevented from exceeding its limit dy dt 1 T Lmax ( ) y = Ku K + (except as indicated below) u y 1 sT Lmin dy dt 1 T ( ) = If L y L then normal Ku y min max dy dt dy dt = If y L then y=L and if > 0 then u 0 max max = If y L then y=L and if < 0 then u 0 min min 18
Lead-Lag Non-Windup Limits There is not a unique way to implement non-windup limits for a lead-lag. This is the one from IEEE 421.5-1995 (Figure E.6) T2 > T1, T1 > 0, T2 > 0 If y > A, then x = A If y < B, then x = B If A y B, then x = y 19
Ignored States When integrating block diagrams often states are ignored, such as a measurement delay with TR=0 In this case the differential equations just become algebraic constraints Example: For block at right, as T 0, v=Ku Lmax K + v u y 1 sT Lmin With lead-lag it is quite common for TA=TB, resulting in the block being ignored 20
IEEE T1 Example Assume previous GENROU case with saturation. Then add a IEEE T1 exciter with Ka=50, Ta=0.04, Ke=-0.06, Te=0.6, Vrmax=1.0, Vrmin= -1.0 For saturation assume Se(2.8) = 0.04, Se(3.73)=0.33 Saturation function is 0.1621(Efd-2.303)2 (for Efd > 2.303); otherwise zero Efd is initially 3.22 Se(3.22)*Efd=0.437 (Vr-Se*Efd)/Ke=Efd Vr =0.244 Vref = 2.44/Ka +Vt = 0.0488 + 1.0946=1.1434 21
IEEE T1 Example For 0.1 second fault (from before), plot of Efd and the terminal voltage is given below Initial V4=1.0946, final V4=1.0973 Steady-state error depends on the value of Ka Gen Bus 4 #1 Term. PU Gen Bus 4 #1 Field Voltage (pu) 1.1 3.5 1.05 3.45 3.4 1 3.35 Gen Bus 4 #1 Field Voltage (pu) 0.95 Gen Bus 4 #1 Term. PU 3.3 3.25 0.9 3.2 0.85 3.15 0.8 3.1 3.05 0.75 3 0.7 2.95 0.65 2.9 2.85 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 Time Time Gen Bus 4 #1 Term. PU Gen Bus 4 #1 Field Voltage (pu) 22
IEEE T1 Example Same case, except with Ka=500 to decrease steady-state error, no Vr limits; this case is actually unstable Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term. PU 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 1.15 1.1 1.05 Gen Bus 4 #1 Field Voltage (pu) 1 Gen Bus 4 #1 Term. PU 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 Time Time Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term. PU 23
IEEE T1 Example With Ka=500 and rate feedback, Kf=0.05, Tf=0.5 Initial V4=1.0946, final V4=1.0957 Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term. PU 8 1.1 7.5 1.05 7 1 6.5 Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term. PU 0.95 6 0.9 5.5 0.85 5 0.8 4.5 4 0.75 3.5 0.7 3 0.65 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 Time Time Gen Bus 4 #1 Field Voltage (pu) Gen Bus 4 #1 Term. PU 24
WECC Case Type 1 Exciters In a recent WECC case with 2782 exciters, 58 are modeled with the IEEE T1, 257 with the EXDC1 and none with the ESDC1A Graph shows KE value for the EXDC1 exciters in case; about 1/3 are separately excited, and the rest self excited Value of KE equal zero indicates code should set KE so Vr initializes to zero; this is used to mimic the operator action of trimming this value Ke 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 Ke 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 20 40 60 80 100 120 140 160 180 200 220 240 Ke 25
DC2 Exciters Other dc exciters exist, such as the EXDC2, which is quite to the EXDC1; about 41 WECC exciters are of this type Vr limits are multiplied by the terminal voltage Image Source: Fig 4 of "Excitation System Models for Power Stability Studies," IEEE Trans. Power App. and Syst., vol. PAS-100, pp. 494-509, February 1981 26
ESDC4B Newer dc model introduced in 421.5-2005 in which a PID controller is added; might represent a retrofit Image Source: Fig 5-4 of IEEE Std 421.5-2005 27
Desired Performance A discussion of the desired performance of exciters is contained in IEEE Std. 421.2-1990 Concerned with large signal performance: large, often discrete change in the voltage such as due to a fault; nonlinearities are significant Limits can play a significant role small signal performance: small disturbances in which close to linear behavior can be assumed Increasingly exciters have inputs from power system stabilizers, so performance with these signals is important 28
Transient Response Figure shows typical transient response performance to a step change in input Image Source: IEEE Std 421.2-1990, Figure 3 29
Small Signal Performance Small signal performance can be assessed by either the time responses, frequency response, or eigenvalue analysis Figure shows the typical open loop performance of an exciter and machine in the frequency domain Image Source: IEEE Std 421.2-1990, Figure 4 30
Small Signal Performance Figure shows typical closed-loop performance Peak value of Mp indicates relative stability; too large a value indicates overshoot Note system connection is open We will return to this when we talk about oscillations Image Source: IEEE Std 421.2-1990, Figure 5 31
