Gate Classifications in Digital Logic Design
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Other Gate Types
COE 202
Digital Logic Design
Dr. Aiman El-Maleh
College of Computer Sciences and Engineering
King Fahd University of Petroleum and Minerals
Outline
Gate Classifications: Primitive & Complex gates
Buffer, Tri-State Buffer
Nand Gate
Nor Gate
Two-level implementation using Nand gates
Two-level implementation using Nor gates
XOR gate
XNOR gate
Parity Generation and Checking
Gate classifications
Gate classifications
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Complex gates can implement Boolean functions with
less area and delay than primitive gates.
Primitive Gates
Buffer
A buffer is a gate with the function F = X:
In terms of Boolean logic, a buffer is the same as a direct
connection!
So why use it?
A buffer is an electronic amplifier that can be used to:
Improve circuit voltage levels e.g. of a received signal
Increase current drive capability (i.e. get a larger fan out)
Introduce desirable circuit delay
Tri-State Outputs
Q. Can the outputs of 2 ICs, or 2
gates, be directly connected?
A.
Generally, No!!! This is only
possible if special types of gates
are used.
Q. Why can’t the outputs of 2
normal gates be directly
connected?
A.
Because this causes a
Short
Circuit
that results in huge current
flow with a subsequent potential for
damaging the circuit.
Tri-State Outputs
This is obvious since one output may be at logic 1 (High
voltage), while the other output may be at logic 0 (Low
voltage).
Furthermore, the common voltage level of the shorted
outputs will most likely fall in the invalid range of voltage
levels.
Q. What are the types of IC output pins that can be
directly connected?
A.
These are pins/gates with special output drivers. The
two main types are:
Open-Collector outputs.
Outputs with
Tri-State
capability.
Gates with Tri-State Outputs
These gates can be in one of 2 possible states:
1. An enabled state where the output may assume one of two
possible values:
Logic 0 value (low voltage)
Logic 1 value (high voltage)
2. A disabled state where the gate output is in the Hi-impedance
(Hi-Z) state. In this case, the gate output is disconnected (open
circuit) from the wire it is driving.
An enable input (E) is used to control the gate into either
the enabled or disabled state.
The enable input (E) may be either active high or active low.
Any gate or IC output may be provided with tri-state
capability.
Condition for Connecting Outputs of
Tri-State Gates
Two or more tri-state outputs may be connected
provided that
at most one
of these outputs is enabled
while all others are in the Hi-Z state.
This avoids conflict situations where one gate output is
high while another is low.
Example:
The circuit performs the function
Example: Tri-State Buffer
F=C’ A + C B
NAND Gate [NOT (AND)]
The basic NAND gate has the following symbol,
AND-Invert (NAND)
NAND represents AND NOT, i. e., an AND function
followed by an inverter (NOT). The symbol shown is an
AND-Invert. The small circle (“bubble”) represents the
invert function.
NAND Gates (continued)
Applying DeMorgan's Law gives Invert-OR (NAND)
This NAND symbol is called Invert-OR, since inputs are
inverted and then ORed together
Note the above symbol is still for a NAND
So a NAND gate can be represented in two different but
equivalent forms:
AND-then-Invert form
Invert-then-OR form
Observations on the NAND Gate
The NAND is not Associative
.
NAND usually does
not
have an operation symbol
defined like the “.” for the AND and the “+” for the OR
This is because NAND is
not
associative and we have
difficulty dealing with non-associative arithmetic!:
≠
Observations on the NAND Gate
i.e. the n-input NAND function
can not
be derived from a
sequence of 2-input NAND operations
But it can be derived as a sequence 2-input AND
operation (which is associative) followed by a
single final
inversion.
The NAND is a Universal Gate
.
Universal gate
– is a gate that can be used to implement
any Boolean function through implementing the
3
basic
logic operations:
(AND, OR, and NOT)
The NAND gate is the natural implementation for the
simplest and fastest electronic circuits.
Observations on the NAND Gate
NOR Gate [NOT (OR)]
The basic NOR gate has the following symbol,
OR-Invert (NOR)
NOR represents OR NOT, i. e., the OR function followed
by a NOT. The symbol shown is an OR-Invert. The
small circle (“bubble”) represents the invert function.
NOR Gate (continued)
Applying DeMorgan's Law gives Invert-AND (NOR)
This NOR symbol is called Invert-AND, since inputs are
inverted and then ANDed together.
Note the above symbol is still for a NOR.
So a NOR gate can be represented in two different but
equivalent forms: OR-then-Invert & Invert-then-AND.
Observations on the NOR Gate
The NOR gate is not Associative
.
NOR usually does not have an operation symbol defined
like the “.” for the AND and the “+” for the OR
This is because NOR is not associative and we have
difficulty dealing with non-associative arithmetic!:
≠
Observations on the NOR Gate
i.e. the n-input NOR function can not be derived from a
sequence of 2-input NOR operations.
But it can be derived as a sequence 2-input OR
operation (which is associative) followed by a single final
inversion.
The NOR gate is a universal gate
.
The NOR gate is another natural implementation for the
simplest and fastest electronic circuits.
Observations on the NOR Gate
Equivalent Gates
Two-Level Implementation using Nand/Nor
We have seen before that Boolean functions in either
SOP or POS forms can be implemented using 2-Level
implementations.
For SOP forms AND gates will be in the first level and a
single OR gate will be in the second level.
For POS forms OR gates will be in the first level and a
single AND gate will be in the second level.
Note that using inverters to complement input variables
is not counted as a level.
We will show that SOP forms can be implemented using
only NAND gates, while POS forms can be implemented
using only NOR gates.
Two-Level Implementation using Nand Gates
Example 1:
Implement the
following SOP function
F = XZ + Y’Z + X’YZ
Introducing two successive
inverters at the inputs of the OR
gate results in the shown
equivalent implementation.
Two successive inverters on the
same line will not have an overall
effect on the logic.
Two-Level Implementation using Nor
Example 2:
Implement the following
POS function
F = (X+Z) (Y’+Z) (X’+Y+Z)
Introducing two successive
inverters at the inputs of the AND
gate results in the shown equivalent
implementation.
Two successive inverters on the
same line will not have an overall
effect on the logic.
Implementation of Multilevel Circuits
using NAND/NOR gates
Start from output toward inputs converting gate by gate
Example: Implement the given circuit using only NAND
gates
Implementation of Multilevel Circuits
using NAND/NOR gates
Example: Implement the given circuit using only NAND
gates
Complex Gates
Exclusive OR (XOR) Gate
The exclusive-OR (XOR), operator uses the symbol
⊕
,
and it performs the following logic operation:
X
⊕
Y
=
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’
+
X
’
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The graphic symbol and truth table of XOR gate is:
The result is 1 only
when either X is equal
to 1 or Y is equal to 1,
but not when both X
and Y are equal to 1.
Exclusive NOR (XNOR) Gate
The exclusive-NOR (XNOR), operator uses the symbol ,
and it performs the following logic operation
The graphic symbol and truth table of XNOR
(Equivalence) gate is shown:
The result is 1 when
either both X and Y
are 0’s or when both
are 1’s. That is why
this gate is often
referred to as the
Equivalence gate
.
2-input XOR / XNOR Gates
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From the K-maps:
From eqns above, note that
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Sum
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Parity
XOR Implementations
The simple SOP implementation uses the following
structure:
A NAND only implementation:
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Properties of XOR/XNOR Operations
Commutativity
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Basic Identities of XOR Operation
Basic Identities of XOR Operation
Proving the above identity is
easier done using graphical
equivalence between gates
Basic Identities of XOR Operation
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Basic Identities of XOR Operation
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XOR for >2 Variables: The Odd Function
The XOR function can be extended to 3 or more literals.
For more than 2 literals, it is called:
Odd function
,
or
modulo 2 sum.
The odd function for
3 inputs and 4 inputs
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The XONR function can be extended to 3 or more
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Even
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Parity Generation and Checking
Exclusive-OR functions are very useful in systems using
parity bits for error-detection.
A parity bit is used for the purpose of detecting errors
during transmission of binary information.
A parity bit is an extra bit included with a binary message
to make the
total number of 1’s in this message
(including the parity bit) either odd or even.
The message, including the parity bit, is transmitted and
then checked at the receiving end for errors.
An error is detected if the checked parity does not
correspond with the one transmitted.
Parity Generation and Checking
The circuit that generates the parity bit at the transmitter
side is called a
parity generator
.
The circuit that checks the parity at the receiver side is
called a
parity checker
.
Parity Generation and Checking
As an example, consider a 3-bit
message to be transmitted
together with an even parity bit.
The three bits, X, Y, and Z,
constitute the message and are
the inputs to the even parity
generator circuit whose output is
the parity bit P.
The 4 bits (X, Y, Z & P) are
transmitted to their destination,
where they are applied to a parity-
checker circuit to check for
possible errors in the transmission.
Parity Generation and Checking
Since the information was
transmitted with even parity,
the received four bits must
have an even number of 1’s.
The parity checker generates
an error signal (C = 1),
whenever the received four
bits have an odd number of
1’s.
Explore the world of gate classifications in digital logic design through topics such as primitive and complex gates, buffer gates, tri-state outputs, and more. Learn about the function and importance of different gate types like NAND, NOR, XOR, XNOR gates, and understand the necessity of using buffers in electronic circuits. Delve into the concepts of gate classifications, primitive gates, and tri-state outputs in COE 202 Digital Logic Design at KFUPM.
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Presentation Transcript
Other Gate Types COE 202 Digital Logic Design Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals
Outline Gate Classifications: Primitive & Complex gates Buffer, Tri-State Buffer Nand Gate Nor Gate Two-level implementation using Nand gates Two-level implementation using Nor gates XOR gate XNOR gate Parity Generation and Checking Other Gate Types COE 202 Digital Logic Design KFUPM slide 2
Gate classifications Gate classifications Primitive gate - a gate that can be described using a single primitive operation type (AND or OR) plus optional inversion(s), e.g. NAND Complex gate - a gate that requires more than one primitive operation to describe it, e.g. XOR Complex gates can implement Boolean functions with less area and delay than primitive gates. Other Gate Types COE 202 Digital Logic Design KFUPM slide 3
Primitive Gates Other Gate Types COE 202 Digital Logic Design KFUPM slide 4
Buffer A buffer is a gate with the function F = X: X F In terms of Boolean logic, a buffer is the same as a direct connection! So why use it? A buffer is an electronic amplifier that can be used to: Improve circuit voltage levels e.g. of a received signal Increase current drive capability (i.e. get a larger fan out) Introduce desirable circuit delay Other Gate Types COE 202 Digital Logic Design KFUPM slide 5
Tri-State Outputs Q. Can the outputs of 2 ICs, or 2 gates, be directly connected? A. Generally, No!!! This is only possible if special types of gates are used. Q. Why can t the outputs of 2 normal gates be directly connected? A. Because this causes a Short Circuit that results in huge current flow with a subsequent potential for damaging the circuit. Other Gate Types COE 202 Digital Logic Design KFUPM slide 6
Tri-State Outputs This is obvious since one output may be at logic 1 (High voltage), while the other output may be at logic 0 (Low voltage). Furthermore, the common voltage level of the shorted outputs will most likely fall in the invalid range of voltage levels. Q. What are the types of IC output pins that can be directly connected? A. These are pins/gates with special output drivers. The two main types are: Open-Collector outputs. Outputs with Tri-State capability. Other Gate Types COE 202 Digital Logic Design KFUPM slide 7
Gates with Tri-State Outputs These gates can be in one of 2 possible states: 1. An enabled state where the output may assume one of two possible values: Logic 0 value (low voltage) Logic 1 value (high voltage) 2. A disabled state where the gate output is in the Hi-impedance (Hi-Z) state. In this case, the gate output is disconnected (open circuit) from the wire it is driving. An enable input (E) is used to control the gate into either the enabled or disabled state. The enable input (E) may be either active high or active low. Any gate or IC output may be provided with tri-state capability. Other Gate Types COE 202 Digital Logic Design KFUPM slide 8
Condition for Connecting Outputs of Tri-State Gates Two or more tri-state outputs may be connected provided that at most one of these outputs is enabled while all others are in the Hi-Z state. This avoids conflict situations where one gate output is high while another is low. Example: The circuit performs the function Other Gate Types COE 202 Digital Logic Design KFUPM slide 9
Example: Tri-State Buffer F=C A + C B Other Gate Types COE 202 Digital Logic Design KFUPM slide 10
NAND Gate [NOT (AND)] The basic NAND gate has the following symbol, AND-Invert (NAND) NAND represents AND NOT, i. e., an AND function followed by an inverter (NOT). The symbol shown is an AND-Invert. The small circle ( bubble ) represents the invert function. Other Gate Types COE 202 Digital Logic Design KFUPM slide 11
NAND Gates (continued) Applying DeMorgan's Law gives Invert-OR (NAND) This NAND symbol is called Invert-OR, since inputs are inverted and then ORed together Note the above symbol is still for a NAND So a NAND gate can be represented in two different but equivalent forms: AND-then-Invert form Invert-then-OR form Other Gate Types COE 202 Digital Logic Design KFUPM slide 12
Observations on the NAND Gate The NAND is not Associative. NAND usually does not have an operation symbol defined like the . for the AND and the + for the OR This is because NAND is not associative and we have difficulty dealing with non-associative arithmetic!: Other Gate Types COE 202 Digital Logic Design KFUPM slide 13
Observations on the NAND Gate i.e. the n-input NAND function can not be derived from a sequence of 2-input NAND operations But it can be derived as a sequence 2-input AND operation (which is associative) followed by a single final inversion. The NAND is a Universal Gate. Universal gate is a gate that can be used to implement any Boolean function through implementing the 3 basic logic operations: (AND, OR, and NOT) The NAND gate is the natural implementation for the simplest and fastest electronic circuits. Other Gate Types COE 202 Digital Logic Design KFUPM slide 14
Observations on the NAND Gate Other Gate Types COE 202 Digital Logic Design KFUPM slide 15
NOR Gate [NOT (OR)] The basic NOR gate has the following symbol, OR-Invert (NOR) NOR represents OR NOT, i. e., the OR function followed by a NOT. The symbol shown is an OR-Invert. The small circle ( bubble ) represents the invert function. Other Gate Types COE 202 Digital Logic Design KFUPM slide 16
NOR Gate (continued) Applying DeMorgan's Law gives Invert-AND (NOR) Invert-AND OR-Invert X Y Z = F ( X , Y , Z ) X Z Y This NOR symbol is called Invert-AND, since inputs are inverted and then ANDed together. Note the above symbol is still for a NOR. So a NOR gate can be represented in two different but equivalent forms: OR-then-Invert & Invert-then-AND. Other Gate Types COE 202 Digital Logic Design KFUPM slide 17
Observations on the NOR Gate The NOR gate is not Associative. NOR usually does not have an operation symbol defined like the . for the AND and the + for the OR This is because NOR is not associative and we have difficulty dealing with non-associative arithmetic!: Other Gate Types COE 202 Digital Logic Design KFUPM slide 18
Observations on the NOR Gate i.e. the n-input NOR function can not be derived from a sequence of 2-input NOR operations. But it can be derived as a sequence 2-input OR operation (which is associative) followed by a single final inversion. The NOR gate is a universal gate. The NOR gate is another natural implementation for the simplest and fastest electronic circuits. Other Gate Types COE 202 Digital Logic Design KFUPM slide 19
Observations on the NOR Gate Other Gate Types COE 202 Digital Logic Design KFUPM slide 20
Equivalent Gates Other Gate Types COE 202 Digital Logic Design KFUPM slide 21
Two-Level Implementation using Nand/Nor We have seen before that Boolean functions in either SOP or POS forms can be implemented using 2-Level implementations. For SOP forms AND gates will be in the first level and a single OR gate will be in the second level. For POS forms OR gates will be in the first level and a single AND gate will be in the second level. Note that using inverters to complement input variables is not counted as a level. We will show that SOP forms can be implemented using only NAND gates, while POS forms can be implemented using only NOR gates. Other Gate Types COE 202 Digital Logic Design KFUPM slide 22
Two-Level Implementation using Nand Gates Example 1: Implement the following SOP function F = XZ + Y Z + X YZ Introducing two successive inverters at the inputs of the OR gate results in the shown equivalent implementation. Two successive inverters on the same line will not have an overall effect on the logic. Other Gate Types COE 202 Digital Logic Design KFUPM slide 23
Two-Level Implementation using Nor Example 2: Implement the following POS function F = (X+Z) (Y +Z) (X +Y+Z) Introducing two successive inverters at the inputs of the AND gate results in the shown equivalent implementation. Two successive inverters on the same line will not have an overall effect on the logic. Other Gate Types COE 202 Digital Logic Design KFUPM slide 24
Implementation of Multilevel Circuits using NAND/NOR gates Start from output toward inputs converting gate by gate Example: Implement the given circuit using only NAND gates Other Gate Types COE 202 Digital Logic Design KFUPM slide 25
Implementation of Multilevel Circuits using NAND/NOR gates Example: Implement the given circuit using only NAND gates Other Gate Types COE 202 Digital Logic Design KFUPM slide 26
Complex Gates Other Gate Types COE 202 Digital Logic Design KFUPM slide 27
Exclusive OR (XOR) Gate The exclusive-OR (XOR), operator uses the symbol , and it performs the following logic operation: X Y = X Y + X Y The graphic symbol and truth table of XOR gate is: The result is 1 only when either X is equal to 1 or Y is equal to 1, but not when both X and Y are equal to 1. Other Gate Types COE 202 Digital Logic Design KFUPM slide 28
Exclusive NOR (XNOR) Gate The exclusive-NOR (XNOR), operator uses the symbol , and it performs the following logic operation The graphic symbol and truth table of XNOR (Equivalence) gate is shown: The result is 1 when either both X and Y are 0 s or when both are 1 s. That is why this gate is often referred to as the Equivalence gate. Other Gate Types COE 202 Digital Logic Design KFUPM slide 29
2-input XOR / XNOR Gates - Sum - Parity Y X Y X (X Y) X Y or X Y 1 for different inputs 0 0 1 1 0 1 0 1 0 1 1 0 1 for equal inputs 0 0 1 1 0 1 0 1 1 0 0 1 0 1 2 3 1 1 1 1 The XOR function means: X OR Y, but NOT BOTH XNOR is called the equivalence function, operator ( ). From the K-maps: Y X Y X Y X + = = + X Y X Y X Y From eqns above, note that Other Gate Types COE 202 Digital Logic Design KFUPM slide 30
XOR Implementations The simple SOP implementation uses the following structure: X AND X Y = + X Y X Y X Y Y X OR X Y AND Y Invert-then-AND = OR-Invert A NAND only implementation: Output of top AND : OR X AND = .( ) X X Y + = ( ) X X Y = + Y X 0 X + X Y X = X Y as above AND = X Y Y Other Gate Types COE 202 Digital Logic Design KFUPM slide 31
Properties of XOR/XNOR Operations Commutativity Associativity Other Gate Types COE 202 Digital Logic Design KFUPM slide 32
Basic Identities of XOR Operation Other Gate Types COE 202 Digital Logic Design KFUPM slide 33
Basic Identities of XOR Operation Proving the above identity is easier done using graphical equivalence between gates Other Gate Types COE 202 Digital Logic Design KFUPM slide 34
Basic Identities of XOR Operation Redraw the given circuit using only 2-input XNOR gates. Minimize the number of 2-input XNOR gates used. Other Gate Types COE 202 Digital Logic Design KFUPM slide 35
Basic Identities of XOR Operation Reimplement the circuit given below using minimum number of 2-input XOR gates. Z = [(A B) B] [(A C) B]= = [(A B) B] [(A C) B] = [(A B) B] [(A C) B] = [A] [(A C) B] = B C Other Gate Types COE 202 Digital Logic Design KFUPM slide 36
XOR for >2 Variables: The Odd Function The XOR function can be extended to 3 or more literals. For more than 2 literals, it is called: Odd function, or modulo 2 sum. Distance 2 The odd function for 3 inputs and 4 inputs = + + + X Y Z X Y Z X Y Z X Y Z X Y Z 1s in the K-map correspond to minterms with indices having an odd number of 1s in binary, hence the name. Use to generate even parity bit and to check even parity (output = 1 for parity error) Other Gate Types COE 202 Digital Logic Design KFUPM slide 37
XNOR for >2 Variables:The Even Function The XONR function can be extended to 3 or more literals. For more than 2 literals, it is called: Even function. Distance 2 The odd function for 3 inputs and 4 inputs = + + + X Y Z X Y Z X Y Z X Y Z X Y Z 1s in the K-map correspond to minterms with indices having an even number of 1s in binary, hence the name. Use to generate odd parity bit and to check odd parity (output = 1 for parity error) Other Gate Types COE 202 Digital Logic Design KFUPM slide 38
Parity Generation and Checking Exclusive-OR functions are very useful in systems using parity bits for error-detection. A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the total number of 1 s in this message (including the parity bit) either odd or even. The message, including the parity bit, is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. Other Gate Types COE 202 Digital Logic Design KFUPM slide 39
Parity Generation and Checking The circuit that generates the parity bit at the transmitter side is called a parity generator. The circuit that checks the parity at the receiver side is called a parity checker. Other Gate Types COE 202 Digital Logic Design KFUPM slide 40
Parity Generation and Checking As an example, consider a 3-bit message to be transmitted together with an even parity bit. The three bits, X, Y, and Z, constitute the message and are the inputs to the even parity generator circuit whose output is the parity bit P. The 4 bits (X, Y, Z & P) are transmitted to their destination, where they are applied to a parity- checker circuit to check for possible errors in the transmission. Other Gate Types COE 202 Digital Logic Design KFUPM slide 41
Parity Generation and Checking Since the information was transmitted with even parity, the received four bits must have an even number of 1 s. The parity checker generates an error signal (C = 1), whenever the received four bits have an odd number of 1 s. Other Gate Types COE 202 Digital Logic Design KFUPM slide 42
