Exploring Kubernetes Load Balancing with P4 Intel IPU Team
This presentation delves into Kubernetes load balancing and network functions using P4 Intel IPU technology. It covers service load balancing, control plane overview, P4 program logical view, demo initial setup, evaluation conclusions, and acknowledgements. The team aims to reduce CPU utilization, improve throughput, and prototype network functions like policy and routing. They plan to enhance the load balancer with elastic capabilities based on CPU and memory usage metrics.
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Presentation Transcript
Kubernetes Load-balancing and related network functions using P4 Intel IPU Team (Nupur Jain, Anjali Singhai Jain, Vinoth Kumar Chandra Mohan)
Service Load-Balancing (kubeproxy) Source: https://docs.projectcalico.org/about/about-kubernetes-services
Control Plane Overview Policy Routing CNI Interface Datastore Local DB/etcd Overlay Link Attrib IP in IP Ingress/ Egress ACL CNI IPU Manager IPAM BGP P4-Runtime (P4 Table view) Client OS IKE Kernel k8.p4 Kernel Msg Listner IKE Plugin SAI API OpenConfig API P4Info .(rt) P4 Runtime Server p4c compiler driver Port (.TDI ) p4c compiler driver SAI Adapter to TDI Compiler P4Info (.TDI ) Table Driven Interface C & C++ API QoS (.TDI ) Table TableKey TableData Init DevMgr TdiInfo TableAttributes TableOperations Session Assembler Assembler CRY (.TDI ) Context file IPU TDI Backend .(JSON) P4 QoS CRYPT IPU Manager Assembler HW Target package file (.pkg) HW Pipeline
Demo initial setup Host Pod 0 (iperf client) Pod 1 (iperf client) Pod 2 (iperf Server) Pod 3 (iperf Server) VIP 10.10.100.1 P4 RunTime Server IPU Manager 10.10.10.2 ens801f0v1 10.10.10.1 10.10.10.3 ens801f0v2 10.10.10.4 ens801f0v3 ens801f0v0 PF ens801f0 (PF) IPU Packet Processing Pipeline (k8s-lb.bin)
Evaluation & Conclusion Claim: Large CPU utilization reduction for Host CPUs with comparable throughput for Node local traffic and increase in throughput for Inter-Node traffic. Conclusion: Prototyping effort for other Network functions like policy and advanced routing on IPU are underway that will uncover the overall performance benefits of offloads. Load balancer can be evolved to an elastic load balancer on IPU that uses feedback loop built based on CPU & memory consumption statistics, packet queue build- ups, direct counters to send event to control plane to trigger launching of more replicas on less overloaded nodes. Code will be published here: https://github.com/p4lang/pna/tree/main/examples
Acknowledgements Neha Singh <neha1.singh@intel.com> Intel IPU Group Andy Fingerhut <andy.fingerhut@gmail.com> - Intel IPU Group Alana Sweat <alana.sweat@intel.com> Intel IPU Group
