Verilog Simulation Tools & Verification Overview
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Verilog Simulation
Tools
&
Verification
池翊忞
(Yi-Min Chih)
Outline
One
wire/ Two wire
Verilog Procedural Interface/ nicotb
2
One wire/ Two wire
3
One Wire
4
Slave receive data when data ready.
Lost
the
data if salve is busy.
Master
Slave
ready
data
Two Wire
5
Master will hold the data when slave is not ack.
Master
Slave
ready
data
ack
Nicotb
6
UVM (Universal Verfication Methodology).
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h
.
)
What Forms Verification?
7
https://verificationacademy.com
Generate Golden Data
Your RTL
Drive data to
input ports
Monitor output ports
and collect data
The non-RTL parts can be implemented without Verilog!
This is usuallyed called co-simulation (co-sim).
The Non-RTL Parts
8
Instantiate (make a copy of) your module.
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.
Golden (Mostly text file in Verilog, or programmatically when co-simed.)
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Brief Conclusions - A Testbench Must
9
Verilog provide external C accesses through VPI.
https://en.wikipedia.org/wiki/Verilog_Procedural_Interface
Based on C, people develops Java, Python... versions.
AFAIK, there are quite a lot Python based frameworks.
myhdl:
https://github.com/myhdl/myhdl
cocotb:
https://github.com/potentialventures/cocotb
nicotb:
https://github.com/johnjohnlin/nicotb
No Need for Verify RTL with Verilog
10
We focus on this today.
Bridging Python and Verilog (Events)
Add these lines in Python
○
rst_out_ev, ck_ev = CreateEvents(["
rst_out
", "
ck_ev
",])
Add this lines in Verilog
○
`Pos(
rst_out
, rst)
`PosIf(
ck_ev
,
clk
, rst)
This means, whenever a
clk
posedge in Python,
ck_ev
is triggered
Mostly your submodules use 1 reset and clock and you just copy it.
That is,
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Bridging Python and Verilog (Wires)
●
API to connect Verilog wires
○
my_data_bus = CreateBus
es
((
("", "a_signal", (4,2)),("dut", "sig"),))
The Verilog to be connected
○
logic [7:0] a_signal [4][2];
DUT my_dut(
.clk(clk),
.sig(sig)
)
12
hierarchy: toplevel → ""
name: a_signal
shape: (4,2)
Bridging Python and Verilog (Wires)
API to connect Verilog wires
○
my_data_bus = CreateBus
es
((
("", "a_signal", (4,2)),("dut", "sig"),))
The Verilog to be connected
○
logic [7:0] a_signal [4][2];
DUT dut(
.clk(clk),
.sig(sig)
)
13
hierarchy: "dut" (nested: "dut.a.b")
name: sig
shape: not a array
First, you need to create the buses
(
irdy
,
iack
,
iint
)
= CreateBus
es
(
[
(("dut", "irdy"),
)
,
(("dut", "iack"),
)
,
(("dut", "iint "),
)
,])
Then, construct the classes in Python
master = TwoWire.Master(irdy, iack, iint, ck_ev, A=1, B=5)
master_data = master.values
Convert Bus into Protocol
(Master)
14
Convert Bus into Protocol
(Master)
Create transfer function.
def iter():
for i in range(pattern_len):
np.copyto(master_data.iint, pattern[i])
yield master_data
Thread = JoinableFork(master.SendIter(iter()))
yield from Thread.Join()
15
create the buses
(
o
rdy
,
oack
,
oint
)
= CreateBus
es
(
[
(("dut", “
o
rdy")
,
)
,
(("dut", “
o
ack")
,
)
,
(("dut", “
o
int ")
,
)
,])
Then, construct the classes in Python
scb = Scoreboard("ISE")test = scb.GetTest(f"output")
st = Stacker(1, callbacks=[test.Get])
bg = BusGetter(callbacks=[st.Get])
slave = TwoWire.Slave(
ordy, oack, oint, ck_ev, callbacks=[
bg
.Get]
)
Convert Bus into Protocol
(Slave)
16
for i in range(golden_len):
test.Expect((golden[i].reshape(1, 1, 1)
Expect(Slave)
17
Check data every time
dimension of data
Constant value
(x, ) = CreateBuses([((“dut”, “x”),),])
x.values[0][0] = x_data
x.Write()
18
Simulation finish
for i in range(100):
yield ck_ev
assert st.is_clean
FinishSim()
19
●
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e
a
b
e
h
i
n
d
S
y
s
t
e
m
V
e
r
i
l
o
g
U
V
M
.
With Python, you can do the same thing much easily.
We introduce Nicotb today.
Document:
https://johnjohnlin.github.io/nicotb/
And there are many choices.
myhdl:
https://github.com/myhdl/myhdl
cocotb:
https://github.com/potentialventures/cocotb
Conclusions
20
The End
Learn about Verilog simulation tools, verification methodologies, procedural interfaces, and co-simulation techniques. Understand the role of testbenches, driving data, monitoring output, and comparing results for effective verification in Verilog. Explore bridging Python with Verilog for event handling.
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Presentation Transcript
Verilog Simulation Tools &Verification (Yi-Min Chih)
Outline One wire/ Two wire Verilog Procedural Interface/ nicotb 2
One Wire Slave receive data when data ready. Lost the data if salve is busy. ready Master Slave data 4
Two Wire Master will hold the data when slave is not ack. ready ack Master Slave data 5
Nicotb 6
What Forms Verification? UVM (Universal Verfication Methodology). (We usually call this overall platform as testbench.) Your RTL https://verificationacademy.com Generate Golden Data Monitor output ports and collect data Drive data to input ports 7
The Non-RTL Parts The non-RTL parts can be implemented without Verilog! This is usuallyed called co-simulation (co-sim). 8
Brief Conclusions - A Testbench Must Instantiate (make a copy of) your module. Driver to send data. Monitor to receive and collect them. Driver and Monitor might follow specific protocols. The collected data are compared by Scoreboard. Golden (Mostly text file in Verilog, or programmatically when co-simed.) Generated by your RTL module and collected by Monitor. 9
No Need for Verify RTL with Verilog Verilog provide external C accesses through VPI. https://en.wikipedia.org/wiki/Verilog_Procedural_Interface Based on C, people develops Java, Python... versions. AFAIK, there are quite a lot Python based frameworks. myhdl: https://github.com/myhdl/myhdl cocotb: https://github.com/potentialventures/cocotb nicotb: https://github.com/johnjohnlin/nicotb We focus on this today. 10
Bridging Python and Verilog (Events) Add these lines in Python rst_out_ev, ck_ev = CreateEvents(["rst_out", "ck_ev",]) Add this lines in Verilog `Pos(rst_out, rst) `PosIf(ck_ev, clk, rst) This means, whenever a clk posedge in Python, ck_ev is triggered Mostly your submodules use 1 reset and clock and you just copy it. That is, Python yield ck_ev = Verilog @posedge clk 11
Bridging Python and Verilog (Wires) API to connect Verilog wires my_data_bus = CreateBuses(( ("", "a_signal", (4,2)), ("dut", "sig"), )) hierarchy: toplevel "" name: a_signal shape: (4,2) The Verilog to be connected logic [7:0] a_signal [4][2]; DUT my_dut( .clk(clk), .sig(sig) ) 12
Bridging Python and Verilog (Wires) API to connect Verilog wires my_data_bus = CreateBuses(( ("", "a_signal", (4,2)), ("dut", "sig"), )) The Verilog to be connected hierarchy: "dut" (nested: "dut.a.b") name: sig shape: not a array logic [7:0] a_signal [4][2]; DUT dut( .clk(clk), .sig(sig) ) 13
Convert Bus into Protocol(Master) First, you need to create the buses (irdy, iack, iint) = CreateBuses([ (("dut", "irdy"),), (("dut", "iack"),), (("dut", "iint "),),]) Then, construct the classes in Python master = TwoWire.Master(irdy, iack, iint, ck_ev, A=1, B=5) master_data = master.values 14
Convert Bus into Protocol(Master) Create transfer function. def iter(): for i in range(pattern_len): np.copyto(master_data.iint, pattern[i]) yield master_data Thread = JoinableFork(master.SendIter(iter())) yield from Thread.Join() 15
Convert Bus into Protocol(Slave) create the buses (ordy, oack, oint) = CreateBuses([ (("dut", ordy"),), (("dut", oack"),), (("dut", oint "),),]) Then, construct the classes in Python scb = Scoreboard("ISE") test = scb.GetTest(f"output") st = Stacker(1, callbacks=[test.Get]) bg = BusGetter(callbacks=[st.Get]) slave = TwoWire.Slave( ordy, oack, oint, ck_ev, callbacks=[bg.Get] ) 16
Expect(Slave) for i in range(golden_len): test.Expect((golden[i].reshape(1, 1, 1) dimension of data Check data every time 17
Constant value (x, ) = CreateBuses([(( dut , x ),),]) x.values[0][0] = x_data x.Write() 18
Simulation finish for i in range(100): yield ck_ev assert st.is_clean FinishSim() 19
Conclusions Introduce the idea behind SystemVerilog UVM. With Python, you can do the same thing much easily. We introduce Nicotb today. Document: https://johnjohnlin.github.io/nicotb/ And there are many choices. myhdl: https://github.com/myhdl/myhdl cocotb: https://github.com/potentialventures/cocotb 20
