Understanding Flash ADC Architecture and Challenges

Explore the Flash ADC architecture designed by Professor Y. Chiu in Fall 2014, including the Vi reference ladder, thermometer code implementation, and typical CMOS comparators. Learn about the challenges faced in Flash ADC design, such as VFS specifications, comparator requirements, and resolution constraints. Gain insights into latch regeneration techniques and speed linear models for enhancing ADC performance.

• Flash ADC
• Architecture
• Challenges
• CMOS Comparators
• Vi Reference

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1. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Flash ADC 1

2. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Flash ADC Architecture Vi VFS Vi Reference ladder consists of 2N equal size resistors Strobe VFS fs 7 7 Input is compared to 2N-1 reference voltages 6 6 5 Encoder 5 Dout Massive parallelism Very fast ADC architecture 2 1 Throughput = fs Latency = 1 T = 1/fs Complexity = 2N 0 Do 0 2N-1 comparators 2

3. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Thermometer Code Thermometer code VFS Vi b2 b1 b0 Strobe fs 1 0 111 0 1 110 1 1 010 1 1 001 000 2N-1 1-of-n code comparators ROM encoder 3

4. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Flash ADC Challenges VDD = 1.8 V 10-bit 1023 comparators 1mV VFS = 1 V DNL < 0.5 LSB 1 LSB = 1 mV Vos < 0.5 LSB = 0.1-0.2 mV 0.5 mV = 3-5 1V 2N-1 very large comparators Large area, large power consumption Very sensitive design Limited to resolutions of 4-8 bits 4

5. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Flash ADC Challenges 128 32 DNL < 0.5 LSB Vos, max [mV] Large VFS relaxes offset tolerance VFS = 2V 8 Small VFS benefits conversion speed (settling, linearity of building blocks) VFS = 1V 2 0.5 4 6 N [bits] 8 10 5

6. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 A Typical CMOS Comparator VDD Vos derives from: Preamp input pair mismatch (Vth,W,L) PMOS loads and current mirror M3 M4 M5 M6 Vos + - Vo Vo M1 M2 Vi M9 Latch mismatch CI / CF imbalance of M9 Clock routing M7 M8 VSS Preamp Latch Parasitics 6

7. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Latch Regeneration VDD PA tracking Latch reseting Latch regenrating M5 M6 VDD + - Vo Vo + Vo M9 CL CL Vo M7 M8 - Vo VSS VSS Exponential regeneration due to positive feedback of M7 and M8 7

8. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Regeneration Speed Linear Model + + - Vo Vo Vo -1 CL CL CL - gmVo - Vo M7 M8 + = + V V 1 1 V o o = 0 o 1 g /sC + V = V g V /sC m L o o m o L ( ) s = = = g /sC 1 0 s g /C , single RHP pole m L p m L ( ) ( ) ( ) = = V t 0 V t 0 exp t g /C o o m L 8

9. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Reg. Speed Linear Model + - Vo Vo CL CL Vo(t=0) t Vo = 1V M7 M8 Vo 1V 1V 1V 1V Vo(t=0) 100mV 10mV 1mV 100 V t/(CL/gm) 2.3 4.6 6.9 9.2 ( ) = V t C = t ln o L ) ( g V t 0 m o 9

10. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Reg. Speed Linear Model + - M5 M6 Vm Vm M3M4 + - gm5Vm gm5Vm + - Vm Vm =1 R9 2 R9 2 x + - + - Vo Vo Vo Vo M1M2 Vi M9 X -1 gm7 -1 gm7 M7 M8 g R R g 1 = = A A , amplifier. be to m5 9 9 m1 V2 V1 2 g R 2 g g m7 9 m7 m3 ( ) 0 ( ) 0 ( ) 0 = = V V A V A A o i V i V1 V2 ( ) t ( ) 0 ( ) = V V A A exp t g /C o i V1 V2 m L 10

11. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Comparator Metastability T/2 ( ) t ( ) 0 ( ) = V V A A exp t g /C o i V1 V2 m L Curve AV1AV2 10 10 10 10 Vi(t=0) 10 mV 1 2 3 4 + Vo 1 mV 100 V - Vo 10 V Comparator fails to produce valid logic outputs within T/2 when input falls into a region that is sufficiently close to the comparator threshold 11

12. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Comparator Metastability Do Assuming that the input is uniformly distributed over VFS, then j+1 BER= Vi 1 LSB j ( ) t ( ) 0 ( ) = V V A A exp t g /C o i V1 V2 m L Vos Cascade preamp stages (typical flash comparator has 2-3 PA stages) Use pipelined multi-stage latches; PA can be pipelined too Avoid branching off comparator logic outputs 12

13. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Comparator Metastability Vi 1 1 1 0 0 x 100 0 1 011 Logic levels can be misinterpreted by digital gates (branching off, diff. outputs) even a wrong decision is better than no decision! 13

14. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 CI and CF in Latch M5 M6 + - Vo Vo Cgs Cgd CM jump M9 CL CL + Vo M7 M8 - Vo Charge injection and clock feedthrough introduce CM jump in Vo+ and Vo- Dynamic latches are more susceptible to CI and CF errors 14

15. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Dynamic Offset of Latch Dynamic offset derives from: Imbalanced CI and CF Imbalanced load capacitance Mismatch b/t M7 and M8 Mismatch b/t M5 and M6 Clock routing + Vo - Vo 0.5V CM jump 50mV offset 10% imbalance Dynamic offset is usually the dominant offset error in latches 15

16. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Typical CMOS Comparator VDD Input-referred latch offset gets divided by the gain of PA M3 M4 M5 M6 Vos Preamp introduces its own offset (mostly static due to Vth, W, and L mismatches) + - Vo Vo M1 M2 Vi M9 M7 M8 PA also reduces kickback noise VSS Preamp Latch Kickback noise disturbs reference voltages, must settle before next sample 16

17. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Comparator Offset VDD Differential pair mismatch: M3 M4 M5 M6 2 2 1 W L Vos ( ) 2 2 2 = + + + - V V V Vo Vo M1 M2 os th ov 4 W L Vi M9 M7 M8 g R g = = A A m5 g 9 R m1 V2 V1 2 g VSS m7 9 m3 Preamp Latch 2 2 2 2 + V os,34 V os,56 V V Total input-referred comparator offset: 2 2 os, dyn A os,78 A = + + + V os,12 V os 2 2 2 2 2 A A A V1 V1 V2 V1 V2 17

18. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Matching Properties Suppose parameter P of two rectangular devices has a mismatch error of P. The variance of parameter P b/t the two devices is 2 A 1st term dominates for small devices ( ) 2 = + 2 2 S D , P P P WL where, W and L are the effective width and length, D is the distance 2 A WL ( ) 2 2 2 Threshold: V = +S D Vth th Vth ( )= 2 2 2 A WL + 2 2 Current factor: S D Ref: M. J. M. Pelgrom, et al., Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989. 18

19. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Why Large Devices Match Better? R1 R2 W X X X X X X X X L 10 identical resistors L W L W = = = R R with std R R 10 10R with std , 1 S R1 2 S 1 R2 10 = = = 2 2 2 10 10 R2 R R1 R2 R1 j = j 1 10 10R 1 10 1 A 1 WL R R R Spatial averaging = = = R2 R1 R1 R 2 1 1 19

20. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 ADC Input Capacitance 2 A WL ( ) = m = 2 2 V C 10 fF/ Vth th g N = 6 bits 63 comparators N (bits) # of comp. Cin (pF) 3.9 VFS = 1 V = LSB/4 1 LSB = 16 mV 6 63 = 4 mV 8 255 250 AVT0 = 10 mV m L = 0.24 m, W = 26 m 10 1023 ??! Small Vos leads to large device sizes, hence large area and power Large comparator leads to large input capacitance, difficult to drive and difficult to maintain tracking bandwidth 20

21. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Flash ADC Errors 21

22. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Distributed Parallel Processing Vi VFS Vi Strobe SHA-less VFS fs 7 Signal and clock propa- gation delay 7 6 6 5 2N-1 PAs + latches must be matched Encoder 5 Dout 2 Synchronized strobe signal is critical 1 0 Do 0 2N-1 PA + Latch Going parallel is fast, but also gives rise to inherent problems 22

23. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Preamp Input Common Mode PA 1 PA j PA j+1 S1 Sj Vi 1 j VR VR 1 j V V R R Input CM difference creates systematic mismatch (offset, gain, Cin, tracking BW, and CMRR) among preamps 23

24. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Sampling Aperture Error M3 M4 M5 M6 Cgd1 Cgd2 Mode VR M1 M2 Track + - high Vo Vo Vin RS M9 Cgs1 Cgs2 Regen low M7 M8 CS Preamp delay and Vth of sampling switch (M9) are both signal-dependent signal-dependent sampling point (aperture error) A major challenge of distributing clock signals across 2N-1 comparators in flash ADC with minimum clock skew (routing, Vth mismatch of M9, etc.) 24

25. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Nonlinear Input Capacitance Vin, Vout RS Vout Vin Cin(Vout) t Signal-dependent input bandwidth (1/RSCin) introduces distortion 25

26. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Input Signal Feedthrough Vi M3 M4 j VR M1 M2 Vin RS Cgs1 Cgs2 Feedthrough of Vin to the reference ladder through the serial connection of Cgs1 and Cgs2 disturbs the reference voltages 26

27. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Fully-Differential Architecture +VR - +Vi - VR Vi PA Latch VFS doubled 3-dB gain in SNR Better CMRR Noise immunity Input feedthrough cancelled Encoder Dout Cin nonlinearity partially removed Effect of Vcmi diff. mitigated 27

28. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Fully-Differential Comparator M5 M6 M7 M8 M1 M2 M3 M4 + - Vo Vo M9 + + - - Vi VR VR Vi Fully-diff. PA Latch Double-balanced, fully-differential preamp Switches (M7, M8) added to stop input propagation during regeneration Active pull-up PMOS added to the latch 28

29. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 AC-Coupled Preamp Vi C VR Latch X PA PA input node X sees constant bias throughout all preamps Autozeroing eliminates PA offsets (stored in C) Ref: A. G. F. Dingwall, Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter, IEEE Journal of Solid-State Circuits, vol. 14, pp. 926-932, issue 6, 1979. 29

30. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Bubbles (Sparkles) 1 1 0 Vi 0 0 1 100 1 0 011 0 1 010 Static/dynamic comparator errors cause bubbles in thermometer code 30

31. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Bubbles (Sparkles) Vi Vj+1 0 j+1 VR j+1 VR 1 1 LSB j+1 j Vj VR j VR 0 j 1 t t Comparator offset Timing error 31

32. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Bubble-Tolerant Boundary Detector Vi 0 1 1 3-input NAND Detect 011 instead of 01 only 0 1 1 Single bubble correction 0 1 Biased correction 1 1 Ref: J. G. Peterson, A monolithic video A/D converter, IEEE Journal of Solid-State Circuits, vol. 14, pp. 932-937, issue 6, 1979. 32

33. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Built-In Bias A B C D 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 011 Det. 001 Det. Case A 1 2 3 B Fail C Fail D Fail Fail Inspecting more neighboring comparator outputs improves performance 33

34. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Majority Voting * = + + C C C C C C C + + j j 1 j j j 1 j 1 j 1 A B C D 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 Majority voting 011 Det. Case A 1 2 3 B Fail C D Fail Fail Ref: C. W. Mangelsdorf, A 400-MHz input flash converter with error correction, IEEE Journal of Solid-State Circuits, vol. 25, pp. 184-191, issue 1, 1990. 34

35. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Gray Encoding Thermometer Gray Binary = + G T T T T 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 3 5 7 = G T T 2 2 6 = G T 3 4 Only one transition b/t adjacent codes T1 T2 T3 T4 T5 T6 T7 G3G2G1 B3 B2 B1 One comparator output is ONLY used once No branching! Gray encoding fails benignly in the presence of bubbles Codes are also robust over metastability errors 35

36. Data Converters EECT 7327 Flash ADC Professor Y. Chiu Fall 2014 Gray Encoding Thermometer 1 1 1 1 1 Gray Decimal 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 0 13 15 12 = + G T T T T 1 1 3 5 7 Conversion of Gray code to binary code is quite time-consuming quasi Gray code = G T T 2 2 6 = G T 3 4 Ref: Y. Akazawa, et al., A 400MSPS 8b flash AD conversion LSI, in IEEE International Solid-State Circuits Conference, Dig. Tech. Papers, 1987, pp. 98-99. 36