Ultra Low Power ADC for In-Vitro Micro-Electrodes Array
Collaborative research project at TIMA Laboratory in France focusing on developing ultra-low power Analog to Digital Converters (ADC) for in-vitro micro-electrode arrays, aiming to enhance communication with the brain using electronics sensors. The project addresses key limitations such as power dissipation and noise in in-vitro applications, with a focus on power reduction and design innovation. Published research showcases advancements in ADC power scaling and methodology, targeting significant power reduction from 180nm to 65nm technology nodes. Contact details for collaboration provided.
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ULTRA LOW POWER ADC FOR IN-VITRO MICRO-ELECTRODES ARRAY READOUT CHAIN WILLIAM BONTEMS: PHD STUDENT IN TIMA DANIEL DZAHINI : dzahini@univ-grenoble-alpes.fr ; professor + senior designer TIMA LABORATORY / GRENOBLE / FRANCE TIMA: 70 PERMANENT PEOPLE + 50 PHD STUDENTS WORKING IN DIFFERENT ASPECTS OF ELECTRONICS
THE DREAM TO COMMUNICATE WITH OUR BRAIN VIA ELECTRONICS SENSORS One might hear about NEURALINK Company of Elon MUSK futur tests NEUROTECH consortium in Grenoble (France) We present here a collaboration project for very low power Microelectrodes: TIMA Lab. France => Ultra low power specific Analog to Digital Converters (ADC) ETH Z rich, 4058 Basel, Switzerland: =>In Vitro Multi-Functional Microelectrode
PUBLISHED BY ANDREAS HIERLEMANN ET. AL ETH Z RICH SWITZERLAND IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 52, NO. 6, JUNE 2017; P.1576 Bloc diagram: AP=Active Photo sensor Chip micrograph
ULTRA LOW POWER MEA (MICRO ELECTRODE ARRAY) Power dissipation and noise are the key limitations for in-vitro applications The number read-out of channels must increase in the near future Power will limit the life time of embedded device Power will damage the signal to read Power may heat the neurons Our present research presents a gain of 20 for the SAR ADC power; 2 is due too process scaling (180n->65n), but 10 is due to design innovation.
NEW FIGURE OF MERIT IN SAR ADC POWER SCALING: FROM 180nm TO 65nm We target to reduce significantly the power (more than factor 20 for the ADC) Using a new methodology of SAR ADC New ADC design going on in TIMA Lab. 10bits; @11.6KSps 15bits, 7.1 W 180nm 65nm IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 56, NO. 8, AUGUST 2021
CONTACT DETAILS Daniel Dzahini: dzahini@univ-alpes-grenoble.fr University Grenoble Alpes TIMA Laboratory tima.univ-grenoble-alpes.fr Tel. +33 674 6468 47
