Pedestal Subtraction and FIR Technique Implementation in FPGA

The content discusses the implementation of the Pedestal Subtraction and Finite Impulse Response (FIR) techniques in FPGA for processing ADC counts from a single channel. It details the update rules for pedestal values during hit detection, considerations for FIR tap values, and the process of new ADC value calculation post-FIR filtering. The challenges and differences in FPGA implementation for these techniques are explored.

• FPGA Implementation
• Pedestal Subtraction
• FIR Technique
• ADC Processing
• Hit Detection

brennerb Follow

Uploaded on Sep 25, 2024 | 0 Views

Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

Presentation Transcript

1. Software Pedestal Subtraction and FIR

2. Pedestal Subtraction We work on ADC counts from a single channel only Only update when not in a hit (stop updating when sample 5 (configurable) ticks ahead is >10 (configurable-will change to actual threshold we want to use) ADC above current pedestal) Begin updating pedestal again when an ADC value below the pedestal is found (which for our hit-finder must be when a hit has ended (and potentially a little way after that if there was an upward drift in ped during hit) If we are updating pedestal then we increase or decrease pedestal by 1 ADC value each tick (frugal streaming) What issues might arise? How will FPGA implementation be different?

3. FIR We work on (pedestal subtracted) ADC counts from a single channel only Currently get the *value* for each tap from np.round(scipy.signal.firwin()*100) 7 taps (should update to 32?) Cutoff =0.1 Nyquist freq How many taps do we want implemented?

4. FIR We find each new ADC value after filtering by: For each tap find if the ADC sample index ,i, is larger than the tap index, j, (tap index loop nested within sample index loop) If it is: add old ADC value with index i-j to new ADC value If it isn t: add old ADC value with index 0 to new ADC value We will then need to divide the ADC statistics collected for each hit by 100 (the number we multiplied the tap *values* in order to make them int) How will FPGA implementation differ?

5. FIR 0 1,2,3,4,5,6, ,4490 4492 Input[0]*tap[0] Input[4491]*tap[0] Input[0]*tap[1] Input[4490]*tap[1] Input[0]*tap[6] Input[4485]*tap[6] For 7 taps