Transport Layer Parameters and Examples
DAC38RF82 82380 Frame Format
1
Transport Layer Parameters
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Important parameters associated with transport layer include
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L
# of lanes per converter device
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M
# of converters per device
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F
# of octets per frame (per lane)
–
S
# of samples per converter per frame clock cycle
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Hd
High-Density bit which controls whether a sample may
be divided over more lanes
LMFS = 82380
Transport Layer Overview
This chart specifies how samples
map to octets, lanes, etc
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Highest Level
Lowest Level
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L
M
F
S
H
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8
4
0
Transport Layer Example
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Example: 11-bit octal ADC converter
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L = 4, M = 8, F = 4, S = 1, CS = 2
Transport Layer Example
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Example: 12-bit Dual DAC38RF82
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L = 8, M = 2, F = 3, S = 8, Hd = 0
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8
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2
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8
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0
Below 12-bit Dual DAC38RF82 example is only showing Lane 0 and Lane 1 data
CH1 will contain I data, and CH2 will contain Q data
S0 = sample 0, S1 = sample 1, ect…
Lane 0 = CH1 S0 bits [11:4], CH1 S0 bits [3:0], CH1 S1 bits [11:8], CH1 S1 bits [7:0]
F1
F2
F3
F1
F2
F3
Lane 1 = CH1 S2 bits [11:4], CH1 S2 bits [3:0], CH1 S3 bits [11:8], CH1 S3 bits [7:0]
1 Frame with 8 samples ( only 4 samples are shown. The other 4 samples will be on Lanes 2 and 3)
With F = 3, there will be three octets per Frame
S
With F = 3, there will be three octets per lane per Frame. Each octet is 8 bits
unencoded or 10 bits encoded (8b/10b).
With S = 8, there will be 8 samples of data per channel per Frame.
This content delves into the important parameters associated with the transport layer, such as the number of lanes per converter device, the number of converters per device, and the number of octets per frame. It provides examples of how these parameters are configured in different scenarios, showcasing the mapping of samples to octets, lanes, and more. Through detailed explanations and visual aids, readers can grasp the intricacies of transport layer communication.
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Presentation Transcript
Transport Layer Parameters Important parameters associated with transport layer include L M F S Hd # of lanes per converter device # of converters per device # of octets per frame (per lane) # of samples per converter per frame clock cycle High-Density bit which controls whether a sample may be divided over more lanes LMFS = 82380
Transport Layer Overview This chart specifies how samples map to octets, lanes, etc
Example of LMFSHd = 44840 Highest Level Lowest Level 4
Transport Layer Example Example: 11-bit octal ADC converter L = 4, M = 8, F = 4, S = 1, CS = 2
Transport Layer Example Example: 12-bit Dual DAC38RF82 L = 8, M = 2, F = 3, S = 8, Hd = 0
Transport Layer Example L = 8, M = 2, F = 3, S = 8, Hd = 0 Below 12-bit Dual DAC38RF82 example is only showing Lane 0 and Lane 1 data CH1 will contain I data, and CH2 will contain Q data S0 = sample 0, S1 = sample 1, ect Lane 0 = CH1 S0 bits [11:4], CH1 S0 bits [3:0], CH1 S1 bits [11:8], CH1 S1 bits [7:0] F1 F2 F3 Lane 1 = CH1 S2 bits [11:4], CH1 S2 bits [3:0], CH1 S3 bits [11:8], CH1 S3 bits [7:0] F1 F2 F3 S 1 Frame with 8 samples ( only 4 samples are shown. The other 4 samples will be on Lanes 2 and 3) With F = 3, there will be three octets per Frame
With F = 3, there will be three octets per lane per Frame. Each octet is 8 bits unencoded or 10 bits encoded (8b/10b). With S = 8, there will be 8 samples of data per channel per Frame.
