Status Update on PMTs and Front-End Boards for RICH Detector

 
RICH TDAQ STATUS
 
F. Bucci, R. Ciaranfi, M. Lenti, M. Piccini, C. Santoni
 
TDAQ WG, 02/09/2014
 
02/09/2014
 
F. Bucci
 
1
 
PMTS INSTALLATION
 
02/09/2014
 
F. Bucci
 
2
 
 
Saleve lodging disk
 
 
Jura lodging disk
 
Installation of PMTs on the Jura and Saleve lodging disks completed
Looked at the signal shape and measured the rate of each PMT
 
PMTS TEST
 
02/09/2014
 
F. Bucci
 
3
 
 
The HV cables of the PMT dividers were plugged in the HV distribution boards
located  at the same distance as in the experimental area
 
The disks were installed on a light tight box and enlighted with a laser
to look for dead channels
 
 
FE STATUS AND TEST
 
02/09/2014
 
F. Bucci
 
4
 
New FE board prototype is ready
Two different setup still under testing
Performances look promising
Order to be placed within the end of the week
Full production should be finished at the end of September
The arrival at CERN is foreseen at the beginning of October
FE boards schedule tight but still feasible
 
SCHEDULE OF INSTALLATION AND
TEST OF PMTS AND FE
 
02/09/2014
 
F. Bucci
 
5
 
 
All the electronics but the FE boards will be carried to CERN next Monday.
In the following  two weeks the PMT lodging disks will be installed in ECN3
and the HV cables will be plugged.
The last week of September the full chain of electronics will be tested by
using a FE board prototype and enlighting the PMTs disk with a laser.
 
 Two different firmware versions has been developed:
 RICH version
 GPURICH version
 
 Most of the firmware is common between the two versions
HITS CLUSTERING
CLUSTERS MERGING
 
 
 
 
CHANNELS INFO
HANDLING
 
 
 
 
CHANNELS INFO
HANDLING
 
RICH
 
RICH
 
GPURICH
 
GPURICH
 
PP FPGA
 
SL FPGA
 
RICH Trigger Firmware Status
 
02/09/2014
 
F. Bucci
 
6
 
RICH 
Firmware
 
 RICH version tested in June
 Primitive production worked fine
 
02/09/2014
 
F. Bucci
 
7
 
0xA0000000
0x4368030b
0x4068
0185
0xB0000002
 
TRIG_IB1:  0x5c
01
00
85
TRIG_IB1:  0x000000
01
TRIG_IB1:  0x5c01000b
TRIG_IB1:  0x00000003
 
PRIMITIVE_DATA:  0x00000000
PRIMITIVE_DATA:  0x000100
61
PRIMITIVE_DATA:  0x000000
00
 
PRIMITIVE_DATA:  0x00000001
PRIMITIVE_DATA:  0x000200c2
PRIMITIVE_DATA:  0x00000000
 
PRIMITIVE_DATA:  0x00000002
PRIMITIVE_DATA:  0x00010024
PRIMITIVE_DATA:  0x00000001
 
PRIMITIVE_DATA:  0x00000003
PRIMITIVE_DATA:  0x00
02
00
85
PRIMITIVE_DATA:  0x000000
01
 
PRIMITIVE_DATA:  0x00000004
PRIMITIVE_DATA:  0x0001000b
PRIMITIVE_DATA:  0x00000003
 
TRIG_IB0:  0x5c0100
61
TRIG_IB0:  0x000000
00
 
0xA0000000
0x42d0
0061
0xB0000002
 
TRIG_IB2:  0x5c0200c2
TRIG_IB2:  0x00000000
TRIG_IB2:  0x5c010024
TRIG_IB2:  0x00000001
TRIG_IB2:  0x5c
01
00
85
TRIG_IB2:  0x000000
01
 
0xA0000000
0x42600124
0x430800c2
0x4078
0185
0x409800c2
0xB0000005
 
0xA0000000
0xB0000001
 
TRIG_IB3:  - - - - - - - - - -
 
RICH 
Firmware
 
From data to primitives:
(data from June test)
 
TDCB 0
 
TDCB 1
 
TDCB 2
 
TDCB 3
 
PP INPUT
 
PP OUTPUT / SL INPUT
 
SL OUTPUT
 
SORTING
 
 
CLUSTERING
 
CLUSTER
MERGING
 
MULTIPLICITY
 
A
VERAGE
FINETIME
 
TIMESTAMP
LSB
 25 
ns
 
02/09/2014
 
F. Bucci
 
8
 
 GPURICH version tested in August
 Primitive production worked fine
 
GPURICH Firmware
TIMESTAMP 25 ns
MULTIPLICITY
CH ID
FINETIME
---
 
SL
OUTPUT
(TDSPY)
 
FIRST
UDP
PACKET
 
SECOND
UDP
PACKET
CH ID
CH ID
 
02/09/2014
 
F. Bucci
 
9
 
 Firmware tested at CERN with emulated data
 Primitive production is working fine (some issues to be addressed)
 Some problems during the integration of the trigger firmware in the
  “generic” one (
talk by Roberto Piandani
)
 Found a working temporary solution
 Final solution is under test
 Rate and latency tests to be done
 
RICH Trigger Firmware Status
 
02/09/2014
 
F. Bucci
 
10
Slide Note
Embed
Share

Updates on the installation and testing of PMTs, including signal shape measurement and dead channel detection, as well as progress on the new front-end board prototype and schedule for full electronics testing. Details on the firmware development and testing for the RICH trigger system. Overview of the upcoming tasks for the installation and testing of PMTs and front-end electronics at CERN.

  • Detector Status
  • PMTs Installation
  • Front-End Boards
  • Firmware Development
  • Electronics Testing

Uploaded on Sep 09, 2024 | 1 Views


Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

E N D

Presentation Transcript


  1. RICH TDAQ STATUS F. Bucci, R. Ciaranfi, M. Lenti, M. Piccini, C. Santoni TDAQ WG, 02/09/2014 02/09/2014 F. Bucci 1

  2. PMTS INSTALLATION Installation of PMTs on the Jura and Saleve lodging disks completed Looked at the signal shape and measured the rate of each PMT Jura lodging disk Saleve lodging disk 02/09/2014 F. Bucci 2

  3. PMTS TEST The disks were installed on a light tight box and enlighted with a laser to look for dead channels The HV cables of the PMT dividers were plugged in the HV distribution boards 02/09/2014 located at the same distance as in the experimental area F. Bucci 3

  4. FE STATUS AND TEST New FE board prototype is ready Two different setup still under testing Performances look promising Order to be placed within the end of the week Full production should be finished at the end of September The arrival at CERN is foreseen at the beginning of October FE boards schedule tight but still feasible 02/09/2014 F. Bucci 4

  5. SCHEDULE OF INSTALLATION AND TEST OF PMTS AND FE All the electronics but the FE boards will be carried to CERN next Monday. In the following two weeks the PMT lodging disks will be installed in ECN3 and the HV cables will be plugged. The last week of September the full chain of electronics will be tested by using a FE board prototype and enlighting the PMTs disk with a laser. 02/09/2014 F. Bucci 5

  6. RICH Trigger Firmware Status Two different firmware versions has been developed: RICH version GPURICH version Most of the firmware is common between the two versions PP FPGA SL FPGA RICH RICH HITS CLUSTERING CLUSTERS MERGING CHANNELS INFO HANDLING GPURICH CHANNELS INFO HANDLING GPURICH 02/09/2014 F. Bucci 6

  7. RICH Firmware RICH version tested in June Primitive production worked fine 02/09/2014 F. Bucci 7

  8. RICH Firmware From data to primitives: (data from June test) PP INPUT PP OUTPUT / SL INPUT SL OUTPUT AVERAGE FINETIME PRIMITIVE_DATA: 0x00000000 PRIMITIVE_DATA: 0x00010061 PRIMITIVE_DATA: 0x00000000 MULTIPLICITY 0xA0000000 0x42d00061 0xB0000002 TRIG_IB0: 0x5c010061 TRIG_IB0: 0x00000000 TIMESTAMP LSB 25 ns TDCB 0 PRIMITIVE_DATA: 0x00000001 PRIMITIVE_DATA: 0x000200c2 PRIMITIVE_DATA: 0x00000000 SORTING TRIG_IB1: 0x5c010085 TRIG_IB1: 0x00000001 TRIG_IB1: 0x5c01000b TRIG_IB1: 0x00000003 0xA0000000 0x4368030b 0x40680185 0xB0000002 TDCB 1 PRIMITIVE_DATA: 0x00000002 PRIMITIVE_DATA: 0x00010024 PRIMITIVE_DATA: 0x00000001 CLUSTERING 0xA0000000 0x42600124 0x430800c2 0x40780185 0x409800c2 0xB0000005 TRIG_IB2: 0x5c0200c2 TRIG_IB2: 0x00000000 TRIG_IB2: 0x5c010024 TRIG_IB2: 0x00000001 TRIG_IB2: 0x5c010085 TRIG_IB2: 0x00000001 CLUSTER PRIMITIVE_DATA: 0x00000003 PRIMITIVE_DATA: 0x00020085 PRIMITIVE_DATA: 0x00000001 MERGING TDCB 2 PRIMITIVE_DATA: 0x00000004 PRIMITIVE_DATA: 0x0001000b PRIMITIVE_DATA: 0x00000003 0xA0000000 0xB0000001 02/09/2014 TRIG_IB3: - - - - - - - - - - TDCB 3 F. Bucci 8

  9. GPURICH Firmware GPURICH version tested in August Primitive production worked fine SL TIMESTAMP 25 ns MULTIPLICITY CH ID OUTPUT (TDSPY) FINETIME CH ID CH ID --- FIRST UDP PACKET SECOND UDP PACKET 02/09/2014 F. Bucci 9

  10. RICH Trigger Firmware Status Firmware tested at CERN with emulated data Primitive production is working fine (some issues to be addressed) Some problems during the integration of the trigger firmware in the generic one (talk by Roberto Piandani) Found a working temporary solution Final solution is under test Rate and latency tests to be done 02/09/2014 F. Bucci 10

Related


More Related Content

giItT1WQy@!-/#giItT1WQy@!-/#giItT1WQy@!-/#giItT1WQy@!-/#