Logic Gates and Large Load Driving in GA-TE Level Design
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UNIT-I
II
GATE
LEVEL
DESIGN
Topics
•
Logic
gates
and
other
complex
gates
•
Switch
logic
•
Alternate
gate
circuits
•
Time
delays
•
Driving
large
capacitive
loads
•
Wiring
capacitances
•
Fan-in
and
fan-out,
Choice
of
layers
NMOS
Gate
construction
A
B
•
NMOS devices
in
series
implement
a
NAND
function
A •
B
A
B
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•
NMOS devices
in
parallel
implement
a NOR
function
A +
B
PMOS
Gate
construction
A
B
•
PMOS
devices in
parallel
implement a NAND
function
B
A
A +
B
A •
B
•
PMOS
devices
in
series
implement
a NOR
function
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Parasitics
and
Performance
•
Consider
the
following
layout:
•
What
is
the
impact
on
performance
of
pa
r
asi
t
i
cs
–
At
point
a
(VDD
rail)?
–
At
point
b
(input)?
–
At
Point
c
(output)?
b
a
c
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Parasitics
and
Performance
•
a
-
power
supply
connections
–
capacitance
-
no
effect
on
delay
–
resistance
-
increa
b
ses
delay
(see
p.
135)
•
minimize
by
reducing
difffusion
length
•
minimize
using
parallel
vias
a
c
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Driving
Large
Loads
•
Off-chip
loads,
long
wires,
etc.
have
high
capacitance
•
Increasing
transistor
size
increases
driving
ability
(and
speed),
but
in
turn
increases
gate
capacitance
•
Solution:
stages
of
progressively
larger
transistors
–
Use
nopt
=
ln(Cbig/Cg).
–
Scale
by
a
factor
of
a=e
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Summary:
Static
CMOS
•
Advantages
–
High Noise
Margins
(VOH=VDD,
VOL=Gnd)
–
No
static
power
consumption
(except
for
leakage)
–
Comparable
rise
and
fall
times
(with
proper
sizing)
–
Robust
and
easy
to
use
•
Disadvantages
–
Large
transistor
counts
(2N
transistors
for
N
inputs)
•
Larger
area
•
More
parasitic loading
(2
transistor
gates
on
each
input)
–
Pullup
issues
•
Lower
driving
capability
of
P
transistors
•
Series
connections
especially
problematic
•
Sizing
helps,
but
increases
loading
on
gate
inputs
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Alternatives
to
Static
CMOS
•
Switch
Logic
•
nmos
•
Pseudo-nmos
•
Dynamic
Logic
•
Low-Power
Gates
Switch
Logic
•
Key
idea:
use
transistors
as
switches
•
Concern:
switches are
bidirectional
A
N
D
A
B
O
R
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Switch
Logic
-
Pass
Transistors
•
Use
n-transistor
as
“switches”
•
“Threshold
problem”
–
Transistor
switches
off
when
Vgs
<
Vt
–
VDD
input
->
VDD-Vt
output
•
“pecial
gate
needed
to
“restore”
values
I
N
:
V
D
D
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285
A
:
V
D
D
O
U
T
:
V
D
D
-
V
t
n
Switch
Logic
-
Transmission
Gates
A
A
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286
•
Complementary
transistors
-
n
and
p
•
No
threshold
problem
•
Cost:
extra
transistor,
extra
control
input
•
Not
a
perfect
conductor!
A
’
A
’
Switch
Logic
Example
-
2-1
MUX
I
N
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Charge
Sharing
•
Consider
transmission
gates
in
series
–
Each
node
has
parasitic
capacitances
–
Problems
occur
when
inputs
change
to
redistribute
charge
–
Solution:
design
network
so
there
is
always
a
path
from
VDD
or
Gnd
to
output
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288
Aside:
Transmission
Gates
in
Analog
•
Transmission
Gates
work
with
analog
values,
too!
•
Example:
Voltage-Scaling
D/A
Converter
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289
NMOS
Logic
•
Used
before
CMOS
was
widely
available
•
Uses
only
n
transistors
–
Normal
n
transistors
in
pull-
down
network
–
depletion-mode
n
transistor
(Vt
<
0)
used
for
pull-up
–
"ratioed
logic"
required
•
Tradeoffs:
–
Simpler
processing
–
Smaller
gates
–
higher
power!
–
Additional
design
considerations
for
ratioed
logic
P
a
s
s
i
v
e
P
u
l
l
u
p
D
e
v
i
c
e
:
d
e
p
l
e
t
i
o
n
M
o
d
e
n
-
t
r
a
n
s
i
s
t
o
r
(
V
t
<
0
)
O
U
T
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P
u
l
l
d
o
w
n
N
e
t
w
o
r
k
Pseudo-nmos
Logic
•
Same
idea,
as
nmos,
but
use
p-
transistor
for
pullup
•
"ratioed
logic"
required
for
proper
design
(more
about
this
next)
•
Tradeoffs:
–
Fewer
transistors
->
smaller
gates, esp.
for
large
number
of
inputs
–
less
capacitative
load
on
gates
that
drive
inputs
–
larger
power
consumption
–
less
noise
margin
(VOL
>
0)
–
additional
design
considerations due
to
ratioed
logic
P
a
s
s
i
v
e
P
u
l
l
u
p
D
e
v
i
c
e
:
P
-
T
r
a
n
s
i
s
t
o
r
O
U
T
P
u
l
l
d
o
w
n
N
e
t
w
o
r
k
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Rationed
Logic
for
Pseudo-nmos
•
Approach:
–
Assume
VOUT=VOL
=0.25*VDD
–
Assume
1
pulldown
transistor
is
on
–
Equate
currents
in
p, n
transistors
–
Solve
for
ratio
between
sizes
of
p,
n
transistors
to
get
these
conditions
n
e
c
essa
r
y
f
or
–
Furth
e
r
c
a
l
cul
a
ti
ons
series
connections
I
dn
I
pn
1
k'
W
n
n
L
n
g
s
,
n
tn
2
V
V
2
1
k'
W
p
p
L
p
g
s
,
p
t
p
d
s
,
p
d
s
,
p
2
V
V
V
V
2
(EQ
3
21)
2
W
p
Wn
Ln
L
p
3.9
(EQ
3
22)
Assu
min
g V
DD
3.3V
I
dp
O
U
T
P
u
l
l
d
o
w
n
N
e
t
w
o
r
k
I
dn
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292
DCVS
Logic
•
DCVS
-
Differential
Cascode
Voltage
Switch
•
Differential
inputs,
outputs
•
Two
pulldown
networks
•
Tradeoffs
–
Lower
capacitative
loading
than
static
CMOS
–
No
ratioed
logic
needed
–
Low
static
power
consumption
–
More
transistors
–
More
signals
to
route
between
gates
O
U
T
P
u
l
l
d
o
w
n
N
e
t
w
o
r
k
O
U
T
’
O
U
T
’
P
u
l
l
d
o
w
n
N
e
t
w
o
r
k
O
U
T
A
B
C
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A
’
B
’
C
’
P
u
l
l
d
o
w
n
N
e
t
w
o
r
k
C
S
A
B
C
Dynamic
Logic
•
Key
idea:
Two-step
operation
–
precharge
-
charge
CS
to
logic
high
–
evaluate
-
conditionally
discharge
CS
•
Control
-
precharge
clock
f
S
t
o
r
a
g
e
N
o
d
e
S
t
o
r
a
g
e
C
a
p
a
c
i
t
a
n
c
e
P
r
e
c
h
a
r
g
e
S
i
g
n
a
l
P
r
e
c
h
a
r
g
e
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E
v
a
l
u
a
t
e
P
r
e
c
h
a
r
g
e
Domino
Logic
•
Key
idea:
dynamic
gate
+
inverter
•
Cascaded
gates
-
“monotonically
increasing”
C
S
P
u
l
l
d
o
w
n
N
e
t
w
o
r
k
B
C
i
n
4
x
1
x
2
x
3
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Domino
Logic
Tradeoffs
•
Fewer
transistors
->
smaller
gates
•
Lower
power
consumption
than
pseudo-nmos
•
Clocking
required
•
Logic
not
complete
(AND,
OR,
but
no
NOT)
In GA-TE Level Design, the topics cover logic gates, complex gates, switch logic, gate circuits, timedelays, driving capacitive loads, wiring capacitances, fan-in and fan-out, choice of layers, NMOS and PMOS gate constructions, parasitics and performance impact, strategies for driving large loads, and a summary of StaticCMOS advantages and disadvantages. Various concepts like implementing NAND and NOR functions using NMOS and PMOS devices, understanding the impact of parasitics on performance, and dealing with capacitance when driving large loads are discussed in detail.
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Presentation Transcript
UNIT-III GA TE LEVELDESIGN Topics Logic gates and other complexgates Switchlogic Alternate gatecircuits Timedelays Driving large capacitiveloads Wiringcapacitances Fan-in and fan-out, Choice oflayers 6/3/2015 274
NMOS Gate construction NMOS devices in series implement a NAND function A B A B F A 0 0 1 0 1 1 B 1 0 1 1 1 0 NMOS devices in parallel implement a NOR function A B F A + B 0 0 1 A B 0 1 0 1 0 0 0 1 1 275 6/3/2015
PMOS Gateconstruction PMOS devices in parallel implement a NAND function A B F 0 0 1 A B 0 1 1 1 0 1 A B 1 1 0 PMOS devices in series implement a NOR function A B F 0 0 1 B 0 1 0 A 1 0 0 0 A +B 1 1 276 6/3/2015
Parasitics andPerformance Consider the followinglayout: What is theimpact on performanceof parasitics At point a (VDDrail)? At point b(input)? At Point c(output)? a b c 6/3/2015 277
Parasitics andPerformance a - powersupply connections capacitance -no effect ondelay resistance -increabses delay (see p.135) minimize byreducing difffusionlength minimizeusing parallel vias a c 6/3/2015 278
Driving LargeLoads Off-chip loads, long wires, etc. have highcapacitance Increasing transistor size increases driving ability (and speed), but in turn increases gatecapacitance Solution: stages of progressively largertransistors Use nopt =ln(Cbig/Cg). Scale by a factor of a=e 6/3/2015 281
Summary: StaticCMOS Advantages High Noise Margins (VOH=VDD,VOL=Gnd) No static power consumption (except forleakage) Comparable rise and fall times (with propersizing) Robust and easy to use Disadvantages Large transistor counts (2N transistors for Ninputs) Largerarea More parasitic loading (2 transistor gates on eachinput) Pullupissues Lower driving capability of Ptransistors Series connections especially problematic Sizing helps, but increases loading on gateinputs 6/3/2015 282
Alternatives to StaticCMOS SwitchLogic nmos Pseudo-nmos Dynamic Logic Low-PowerGates 6/3/2015 283
SwitchLogic Key idea: use transistors asswitches Concern: switches arebidirectional A B AND OR 6/3/2015 284
Switch Logic - PassTransistors Use n-transistor as switches Thresholdproblem Transistor switches off when Vgs <Vt VDD input -> VDD-Vtoutput pecial gate needed to restore values IN: VDD OUT: VDD-Vtn A: VDD 6/3/2015 285
Switch Logic - TransmissionGates Complementary transistors - n andp No threshold problem Cost: extra transistor, extra controlinput Not a perfectconductor! A A A A 6/3/2015 286
Switch Logic Example - 2-1MUX IN 6/3/2015 287
ChargeSharing Consider transmission gates in series Each node has parasitic capacitances Problems occur when inputs change to redistribute charge Solution: design network so there is always a path from VDD or Gnd to output 6/3/2015 288
Aside: Transmission Gates inAnalog TransmissionGates work with analog values,too! Example: Voltage-Scaling D/AConverter 6/3/2015 289
NMOSLogic Used before CMOS was widely available Uses only n transistors Normal n transistors inpull- downnetwork depletion-mode ntransistor (Vt < 0) used forpull-up "ratioed logic"required Tradeoffs: Simplerprocessing Smallergates higherpower! Additionaldesign considerations for ratioedlogic Passive PullupDevice: depletion Mode n-transistor (Vt < 0) OUT Pulldown Network 290 6/3/2015
Pseudo-nmosLogic Same idea, as nmos, but use p- transistor forpullup "ratioed logic" required for proper design(more about this next) Tradeoffs: Fewer transistors -> smaller gates,esp.for largenumber of inputs less capacitative load ongates that driveinputs larger powerconsumption less noise margin (VOL >0) additional design considerations due to ratioed logic Passive PullupDevice: P-Transistor OUT Pulldown Network 6/3/2015 291
Rationed Logic for Pseudo-nmos Approach: Assume VOUT=VOL=0.25*VDD Assume 1 pulldown transistor ison Equate currents in p, ntransistors Solve for ratio between sizes of p, n transistors to get theseconditions necessary for Further calculations seriesconnections Idn = Ipn ( 2 2 Idp OUT Pulldown Network Idn 2(V (EQ 3 21) Wp V )2 =1k' V )V Wn 1k' V2 gs,n V nLn pLp tn gs,p tp ds,p ds,p Wp L p 3.9 (EQ 3 22) Assu ming VDD=3.3V WnLn 6/3/2015 292
DCVSLogic DCVS - Differential Cascode VoltageSwitch Differential inputs,outputs Two pulldown networks Tradeoffs Lower capacitativeloading than staticCMOS No ratioed logicneeded Low staticpower consumption More transistors More signals toroute between gates OUT OUT A B C A B C OUT OUT Pulldown Network Pulldown Network 6/3/2015 293
DynamicLogic Key idea: Two-stepoperation precharge - charge C S to logichigh evaluate - conditionally dischargeC S Control - precharge clockf StorageNode CS Precharge Signal Storage Capacitance Pulldown Network B A C Precharge Evaluate Precharge 6/3/2015 294
DominoLogic Key idea: dynamic gate +inverter Cascaded gates - monotonically increasing CS Pulldown Network B C in4 x1 x2 x3 6/3/2015 295
Domino LogicTradeoffs Fewer transistors -> smallergates Lower power consumption thanpseudo-nmos Clockingrequired Logic not complete (AND, OR, but noNOT) 6/3/2015 296
