FPGA for Underwater Communication Project Overview

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This project, led by Pradyumna (Prad) Kadambi with mentor Cody Youngbull, aims to develop a robust high-speed underwater communication system using Field Programmable Gate Arrays (FPGA). The project addresses the slow and cumbersome nature of current underwater communication methods, with a focus on applications in environmental monitoring, structural monitoring, oil and gas defense. The system architecture involves an analog front end, FPGA processing, microcontroller interface, and peripherals for data processing and communication. Future goals include expanding to networked sensing arrays and improving error correction, distance, and speed.

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  1. FPGA for Underwater Communication Pradyumna (Prad) Kadambi Mentor: Cody Youngbull April 13, 2015

  2. Motivation Current underwater communication can be slow and cumbersome Need for environmental/structural monitoring Oil and Gas Defense Goal: Create a robust, high speed underwater communication system Optical communication

  3. Field Programmable Gate Array (FPGA) Advantages: Massively parallel Immense flexibility No fixed hardware structure All algorithms are implemented in hardware! Disadvantages: FPGA development can be lengthy Programming FPGA is more involved than programming a microcontroller ni.com

  4. System Architecture Analog front end Required to detect optical signal Analog to digital conversion (ADC) FPGA Process detected signal Decode received signal to intelligible letters and numbers Microcontroller Interface with communication ports, storage devices Peripherals Analog Receiver/ Transmitter FPGA (Data Microcontroller Processing) Peripherals

  5. UART Microcontroller must communicate with FPGA. Universal Asynchronous Receiver Transmitter (UART) UART is simple, has low overhead Only need to transmit Start bit and Stop bit One character is sent every 8 bits embedded.com

  6. FPGA Design Flow 1. Model algorithms in Simulink 2. Simulate and debug algorithms 3. Convert algorithms to HDL Hardware Description Language 4. Simulate and debug HDL 5. Test/debug hardware Often hardware will not match simulation Design is an iterative process digilentinc.com

  7. Current Milestones Fully functional FPGA design Point to point communication Sensor integration

  8. Future Goals Expand on networked sensing arrays Another presenter will be addressing this issue Forward error correction Improve distance Improve speed

  9. Thank You!

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