Amplifier Design Tradeoffs in Semiconductor Technology
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P
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•
Understand the theory behind the relationship between SNR, noise
sources, ADC performance
•
Know how to select the appropriate clocking solution for a given
application
•
Learn about additional techniques for improving sampling clock quality
to the ADC
•
Understand the clocking effects of DACs and the tradeoffs between
jitter and NSD specifications
•
Become familiar with TI’s clocking solutions portfolio
2
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SNR, Noise Sources, and ADC Performance
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Noise
Signal
Noisy Signal
FREQUENCY (Hz)
Signal
Noise Level
In the time domain:
In the frequency domain:
FFT
•
SNR is the ratio of the signal power to the noise power that corrupts the
signal. This parameter does not include harmonic distortion.
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SNR can be increased in the
following ways:
•
Increase signal power
↑
–
Full Scale Range (FSR)
•
Decrease noise power
↓
–
Quantization Noise
–
Clock Jitter
–
ADC Aperture Jitter
–
Thermal Noise
5
Thermal
Clock Jitter
Aperture Jitter
Quantization
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Total SNR can be calculated by the sum of the individual sources:
6
SNR
QUANT
= SNR due to quantization
SNR
JITTER
= SNR due to clock and aperture jitter
SNR
THERM
= SNR due to thermal and transistor noise
•
SNR due to quantization error, assuming a sine wave input:
•
How to determine the required ADC resolution?
–
An N-bit ADC determines the maximum possible SNR for the system
–
Practically, an ADC’s SNR is limited by other factors:
•
Sampling clock jitter
•
ADC jitter and thermal noise
•
Other system noise sources
•
Over-sampling rate and application channel bandwidth
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Noise in an ADC:
•
Track-and-hold is
dominant source
•
Capacitors source
no noise
•
Resistor results in
“kT/C” noise
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Clock jitter
is the random variation of
the clock edge compared to its ideal
point in time
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Theoretical limit of SNR due to jitter:
•
Total jitter is the rms sum of the
individual jitter contributions
–
For ADCs, this is generally the external
clock jitter and aperture jitter
9
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Clock jitter causes imprecise sampling
intervals which results in incorrect
sampling instances and therefore
errors in the sampled signal
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Clock jitter has an increased effect at
higher input frequencies or higher
maximum input slew rates
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.
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Clock jitter
is the jitter contribution from the external clock source and
can be measured by using a phase noise analyzer
•
Aperture jitter
(a.k.a. aperture uncertainty) is the jitter contribution from
the ADC, due to the internal clock buffers. This cannot be measured
directly using a phase noise analyzer.
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The
total clock jitter
is determined by rms sum of all individual
contributions:
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Noise Spectral Density (dBc/Hz)
Frequency (MHz)
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Jitter is a result of noise on the sampling clock. Assuming the wideband
clock noise is relatively low, then the clock jitter is calculated by
integrating the clock phase noise over a specified BW then converting
to seconds.
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Example from previous slide’s phase noise plot:
–
N
= -75.72 dBc/Hz (from 10 kHz to 10 MHz offset)
–
F
clk
= 122.88 MHz
13
Where:
N
= Phase Noise Power (dBc)
f
0
, f
1
= frequency limits of integration
j
= clock jitter
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The target SNR is generally based on the system requirements
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Then ADC aperture jitter and IF center frequency can be used to
calculate the required external clock jitter performance
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Use Jitter Calculator Worksheet:
–
http://www.ti.com/litv/zip/slac133
–
The current worksheet does not account for the contribution from
quantization and thermal noise (see total SNR from earlier)
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Aperture jitter:
j
= 80 fs
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Input Frequency: f
IN
= {10 MHz, 100 MHz}•
SNR from datasheet:
–
Includes effect of thermal and quantization noise, and aperture jitter
–
External clock jitter is negligible since the highest quality source was used
•
Clock source:
–
LMK04803 with 80 MHz VCXO in dual-loop mode
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10 MHz reference from analog input signal generator
–
125 MHz LC bandpass filter on clock signal
–
Phase noise plot on next screen
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114 fs of jitter in integration band of 1 kHz to 40 MHz
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10 MHz Case:
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From datasheet:
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SNR @ 10 MHz = 79 dBFS
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From spreadsheet:
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Total estimated SNR:
100 MHz Case:
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From datasheet:
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SNR @ 100 MHz = 78.2 dBFS
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From spreadsheet
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Total estimated SNR:
18
Assuming -1 dBFS Input
Assuming -1 dBFS Input
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Error: | 79.13 dBFS – 78.98 dBFS | = 0.15 dB
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Error: | 76.83 – 76.73 | = 0.10 dBFS
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The Noise Spectral Density can be approximated by using SNR from
the datasheet at low input frequency:
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Clock noise can also be included in the NSD calculation by using the
total SNR shown previously. It may be beneficial to look at the shape of
the clock noise when considered NSD.
21
Ideal NSD by Quantization Noise:
Actual NSD by SNR at low Fin:
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Improving the Sampling Clock Quality
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Clock sources have wideband noise that will also contribute to the
overall jitter of the clock
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This is can be important since ADCs often have very wide clock input
bandwidths (up to ~ 2 GHz)
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In order to eliminate the wideband noise of the clock source, a filter can
be placed on the clock lines
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A bandpass filter is preferred, but a low pass filter could be acceptable
–
The amount of filtering will vary based on the system requirements
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A tight passband will have more loss which could have additional problems
•
Note that filtering a square wave will produce a sine wave with a slower
slew rate, this may hurt the jitter performance slightly
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Filtering the clock can eliminate clock related spurs, especially those
associated with different frequencies coupling in due to clock isolation
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A square wave clock (e.g. LVPECL) has a very high slew rate, but does
not allow clock filtering as clock harmonics generate the high slew rate
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Filtering the clock removes clock noise, but limits the slew rate
Harmonics
Clock
Noise
Frequency
Bandpass Filter
Frequency
Lower Noise
Slew Rate
Slew Rate
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The plot below has two phase noise measurements overlaid from the
same LMK04803, but the slightly darker trace has a relatively tight LC
band-pass filter on it.
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Note that the overall jitter in the
1 kHz to 40 MHz bandwidth
has actually degraded slightly
for the filtered case due to a
slower slew rate from filtering
out the harmonics.
•
However, the wideband noise
has gone from -163 dBc/Hz
to -174 dBc/Hz. Integrated
over 500 MHz, this will make
a significant difference (~200 fs) and will easily
overcome the added jitter due to a lower slew rate.
25
Higher in-band phase noise
Lower wide-band noise
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Without Filter
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With Filter
Clocking with a sine wave can
reduce clock related spurs.
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The jitter generated by the ADC clock receiver is affected by the clock
slew rate
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Filtering the ADC clock will lower the clock slew rate by removing the
harmonics
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A slower slew rate causes the receiver to be more susceptible to
variations in the zero crossing point
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A faster clock slew rate lowers the jitter due to the receiver voltage
noise
Receiver
noise
V/
t =
slew rate
Receiver Jitter ~ Receiver Noise *
V/
t
Aperture
Jitter
Total Jitter ~
(Clock Jitter
2
+
Receiver Jitter
2
+
Aperture Jitter
2
)
1/2
Clock
Jitter
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For a clock that has ~9 dBm less power, jitter has been increased from
31.52 fs to 72.208 fs
28
6.11 dBm Clock:
-3.35 dBm Clock:
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The traditional SNR due to jitter equation gives the SNR over the entire
Nyquist band, with the jitter measured over a wide clock offset
frequency
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The equation is a function of the analog input frequency and jitter
performance
•
If the ADC clock is already fine tuned to the best jitter performance,
would the only option left to meet the stringent SNR performance is to
adjust the input frequency?
•
If so, what is the point of over-sampling ADCs?
30
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It turns out the SNR equation is also a function of clock frequency as
well. Recall the jitter equation:
•
If we substitute the jitter equation into the SNR equation, we would get
the following:
•
The first term is the inherent integrated noise due to clock noise. The
second term is a correction term. This is important to help us
understand the performance of over-sampling. If over-sampling is used,
the SNR can be improved
31
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The general equation is important because the traditional equation
often simplifies the ADC clock noise floor as an uniform white noise.
•
In reality, the ADC clock usually has better noise behavior as the offset
frequency increases, and also, the clock is often well filtered.
Simplified integrated clock noise
Actual phase noise
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Most importantly, some of the stringent system requirements often are
bandwidth specific. I.e. noise spec over a specific bandwidth.
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For instance, when given a certain blocker signal, the traditional SNR
calculation may overestimate the noise over the bandwidth of the
wanted signal. This may make jitter specification of the clock
impossible to achieve.
33
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Clocking the ADC with a 250MHz
tone + 10MHz noise ranging from
240MHz to 250MHz
(DAC5681 output)
ADS4149 at 250MSPS
Two inputs shown and
overlaid: 10MHz and 100MHz
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20log(250/10) = 28dBc
20log(250/100) = 8dBc
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The total SNR is the vector sum of all individual SNR contributions
•
Similar treatment of clock jitter (integrated phase noise) for SNR limit of
DAC sampled system
37
SNR
QUANT
= SNR due to quantization
SNR
CLK
= SNR due to clock and aperture jitter
SNR
THERM
= SNR due to thermal and transistor noise
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?
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For DACs, generally the noise spectral density (NSD) is more important
than overall SNR
–
The shape of the NSD around the carrier must meet mask requirements
–
When SNR is required, customer’s often limit the bandwidth of the
transmitted signal by a bandpass or lowpass filter
•
For this reason, newer datasheets report NSD rather than SNR
38
fs = 1GSPS
f out = 20MHz
Noise
Signal
•
DAC output noise is comprised of
–
Quantization noise
–
Thermal noise
–
Jitter noise
–
Data dependent noise
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?
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In real systems, there is often tight filtering around the band of interest,
where all the noise outside of that band is filtered out.
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Rather than showing the SNR of the signal in the first Nyquist zone, it is
more convenient to show the noise power so that the total noise power
in the unfiltered band can be readily calculated
•
For example, consider a DAC3484 running at 1228.8 MSPS with a
band of interest of 100 MHz and the following filters:
–
A 614.4-MHz low-pass filter (passing full first Nyquist zone):
–
A 100-MHz low-pass filter:
39
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The SNR of the DAC can be calculated from the NSD spec
•
The SNR was traditionally defined as the ratio of the power of the
fundamental to the power of the noise integrated over the first Nyquist
zone.
•
It can also be calculated directly in dBFS from the NSD in dBc/Hz
•
Example: DAC3484 running at 1.25 GSPS with 10 MHz output
40
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SNR estimates based on Jitter are good estimates for SNR for the
entire Nyquist band – may be too pessimistic for BW limited
applications.
•
SNR estimates based on NSD (typically measured at some MHz offset)
do not account for close-in phase noise which could affect inband EVM
–
Useful for out of band estimates like ACPR
–
Also useful for transmit mask requirements
•
Using the clock NSD curve and BW limited noise calculations would be
the ideal solution for in-band and out-of-band measurements.
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For both sampled systems of the ADC and DAC the CLK phase noise
will be translated from the clock to the sampled outputs with the
following relationship:
•
All in-band (%EVM, RX
sensitivity) and out-of-band
(ACPR, TX Mask)
measurements can be based
on the measured phase noise
plot of the ADC and DAC clock
source
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At higher frequency offsets where the phase noise of the clock drops
off, the intrinsic noise of the DAC will play a role in the overall noise
floor of the output spectrum
•
Measurements of the CLK NSD and the DAC output NSD show that
there is some discrepancy between the estimates – this is accounted
for by the DAC intrinsic noise due to the Thermal/Device effects
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The Intrinsic DAC noise is frequency dependent and measured at a
particular offset frequency will only be approximately accurate for other
offset frequencies.
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Intrinsic Noise estimates made at 40MHz offset are somewhat accurate
for NSD estimates at the same frequency offset using different clock
sources.
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The intrinsic noise is due to quantization and thermal noise sources
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WCDMA signal 3.84MHz BW, IF=122.88M, Sample rate 983.04Msps,
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Assuming that %EVM is a measure of the SNR of the average inband
signal power to the average inband NSD we can estimate the required
average NSD of the clock (-105.84dBc/Hz avg at DAC output)
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Scale by IF and Sample rate (-87.78dBc/Hz avg at Clock source)
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Average Clock NSD within 3.84MHz around the fundamental clock
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The average clock NSD must be less than the predicted clock NSD to
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WCDMA signal 3.84MHz BW, IF=122.88M, Sample rate 983.04Msps,
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The Clock NSD for both the ACPR and Alt ACPR is given by:
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Clock NSD ACPR = -118dBc/Hz, Clock NSD Alt ACPR = -123dBc/Hz
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Using some common clock sources we can see that the Clock NSD at
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Clock NSD at the ACPR and Alt ACPR offsets that there is negligible
difference between using different clocks at different IF frequencies.
Follows the shape of Intrinsic DAC noise.
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Same results with Alt ACPR.
Delve into the intricate world of amplifier design, as we explore the tradeoffs between weak, moderate, and strong inversion in semiconductor technology. Discover the delicate balance between speed and power efficiency, and uncover the importance of the gm/Id curve in optimizing transistor performance. Gain insights into the critical factors influencing design choices and the impact on overall circuit performance.
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Presentation Transcript
Clocking High Speed Data Converters High Speed Data Converters Authors: Matt Guibord, Marjorie Plisch Presented by: Matt Guibord Applications Engineer High Speed Data Converters 1
Presentation Goals Understand the theory behind the relationship between SNR, noise sources, ADC performance Know how to select the appropriate clocking solution for a given application Learn about additional techniques for improving sampling clock quality to the ADC Understand the clocking effects of DACs and the tradeoffs between jitter and NSD specifications Become familiar with TI s clocking solutions portfolio 2
SNR, Noise Sources, and ADC Performance UNDERSTANDING THE THEORY FOR ADCS 3
Signal-to-Noise Ratio Basics SNR is the ratio of the signal power to the noise power that corrupts the signal. This parameter does not include harmonic distortion. In the time domain: Noise Signal Noisy Signal In the frequency domain: Signal P = 10 log SIGNAL SNR NOISE P Amplitude (dB) = SNR SIGNAL P = NOISE P , , dBm log dBm + 10 10 log NOISE P NOISE P BW , , / dBm dBm Hz Hz Noise Level FREQUENCY (Hz) 4
Maximizing the SNR in an ADC = SNR SIGNAL P NOISE P SNR can be increased in the following ways: , , dBm dBm Quantization Increase signal power Full Scale Range (FSR) Thermal Decrease noise power Quantization Noise Clock Jitter ADC Aperture Jitter Thermal Noise Aperture Jitter Clock Jitter 5
SNR by Individual Contributors Total SNR can be calculated by the sum of the individual sources: = 10 10 1 10 log SNR total SNR SNR SNR QUANT JITTER THERM + + 10 10 10 10 SNRQUANT = SNR due to quantization SNRJITTER = SNR due to clock and aperture jitter SNRTHERM = SNR due to thermal and transistor noise Design Choice ADC Selection Effect on Noise N-bits affects quantization noise, aperture jitter and thermal noise by design Clock jitter Bandwidth over which noise is distributed Sampling Clock Selection Sampling Rate 6
Quantization Noise and SNR SNR due to quantization error, assuming a sine wave input: N SNRQUANT 02 . 6 = . 1 + 76 dB Example: 14-bit converter where N=14: = . 1 + = . 6 02 14 76 86 04 . SNRQUANT dB How to determine the required ADC resolution? An N-bit ADC determines the maximum possible SNR for the system Practically, an ADC s SNR is limited by other factors: Sampling clock jitter ADC jitter and thermal noise Other system noise sources Over-sampling rate and application channel bandwidth 7
Transistor and Thermal Noise and SNR Noise Mechanism Shot Spectral Profile white Source Cause IDC pn-junctions DC bias current is not constant Carriers are trapped and released in a semiconductor Thermal excitation of carriers in a conductor Flicker 1/f 1/f Active devices Thermal T white resistors Noise in an ADC: Track-and-hold is dominant source Capacitors source no noise Resistor results in kT/C noise = 2 2 ( ) ( ) * * v f v f f no R o 2 1 = 4 ( ) * ( ) * ( ) kTR RC 2 2 kT = C 8
Clock Jitter and SNR t=Jitter Clock jitter is the random variation of the clock edge compared to its ideal point in time Clk Theoretical limit of SNR due to jitter: where = = 2 20 log( ) SNR dBc f j in j : IF1 f input frequency in = clock jitter j Total jitter is the rms sum of the individual jitter contributions For ADCs, this is generally the external clock jitter and aperture jitter IF2 2 2 = external aperture + T 9
More on Clock Jitter t=Jitter Clock jitter causes imprecise sampling intervals which results in incorrect sampling instances and therefore errors in the sampled signal Clk Clock jitter has an increased effect at higher input frequencies or higher maximum input slew rates IF1 IF2 10
Sources of Clock Jitter The total clock jitter for an ADC is from the aperture jitter and the external sampling clock jitter. Clock jitter is the jitter contribution from the external clock source and can be measured by using a phase noise analyzer Aperture jitter (a.k.a. aperture uncertainty) is the jitter contribution from the ADC, due to the internal clock buffers. This cannot be measured directly using a phase noise analyzer. Example: aperture jitter for the ADS4249 The total clock jitter is determined by rms sum of all individual contributions: = 2 APERTURE + 2 EXTERNAL TOTAL 11
Example Phase Noise Plot Noise Spectral Density (dBc/Hz) Frequency (MHz) 12
Calculating Jitter from Clock Phase Noise Jitter is a result of noise on the sampling clock. Assuming the wideband clock noise is relatively low, then the clock jitter is calculated by integrating the clock phase noise over a specified BW then converting to seconds. Where: N= Phase Noise Power (dBc) f0, f1= frequency limits of integration j = clock jitter N 2 10 10 = j 2 f clk Example from previous slide s phase noise plot: N = -75.72 dBc/Hz (from 10 kHz to 10 MHz offset) Fclk = 122.88 MHz 75 72 . / dBc 10 Hz 2 10 = = 299 77 . fs ( ) j 2 122 88 . MHz 13
Determining Clock Jitter Requirements The target SNR is generally based on the system requirements Then ADC aperture jitter and IF center frequency can be used to calculate the required external clock jitter performance Use Jitter Calculator Worksheet: http://www.ti.com/litv/zip/slac133 The current worksheet does not account for the contribution from quantization and thermal noise (see total SNR from earlier) 15
Example: ADS5483 (16-bit, 125 MSPS) Aperture jitter: j = 80 fs Input Frequency: fIN = {10 MHz, 100 MHz} SNR from datasheet: Includes effect of thermal and quantization noise, and aperture jitter External clock jitter is negligible since the highest quality source was used Clock source: LMK04803 with 80 MHz VCXO in dual-loop mode 10 MHz reference from analog input signal generator 125 MHz LC bandpass filter on clock signal Phase noise plot on next screen 16
Example: ADS5483 Clock Phase Noise 114 fs of jitter in integration band of 1 kHz to 40 MHz 17
Example: ADS5483 SNR Analysis 10 MHz Case: 100 MHz Case: From datasheet: SNR @ 10 MHz = 79 dBFS From datasheet: SNR @ 100 MHz = 78.2 dBFS From spreadsheet: From spreadsheet Total estimated SNR: Total estimated SNR: 1 1 = = 10 log SNR 10 log SNR ( ) ( ) total total + + 81 16 . 1 101 16 . 1 78 2 . 79 + + 10 10 10 10 10 10 10 10 = = 76 73 . 78 98 . SNR dBFS SNR dBFS total total 18
Example: ADS5483 10 MHz FFT Error: | 79.13 dBFS 78.98 dBFS | = 0.15 dB 19
Example: ADS5483 100 MHz FFT Error: | 76.83 76.73 | = 0.10 dBFS 20
Estimating NSD from SNR The Noise Spectral Density can be approximated by using SNR from the datasheet at low input frequency: Example: from ADS4249 Datasheet with Fs = 250MSPS and N=14: Actual NSD by SNR at low Fin: Ideal NSD by Quantization Noise: = = 10 * log ( ) NSD SNR BW 10 * log ( ) NSD SNR BW 10 10 = 6 = 6 72 8 . 10 * log 125 ( * 10 ) 86 04 . 10 * log 125 ( * 10 ) 10 10 = dBFS 8 . 153 = 167 / Hz / dBFS Hz Clock noise can also be included in the NSD calculation by using the total SNR shown previously. It may be beneficial to look at the shape of the clock noise when considered NSD. 21
Improving the Sampling Clock Quality ADDITIONAL TECHNIQUES 22
A note on clock filtering Clock sources have wideband noise that will also contribute to the overall jitter of the clock This is can be important since ADCs often have very wide clock input bandwidths (up to ~ 2 GHz) In order to eliminate the wideband noise of the clock source, a filter can be placed on the clock lines A bandpass filter is preferred, but a low pass filter could be acceptable The amount of filtering will vary based on the system requirements A tight passband will have more loss which could have additional problems Note that filtering a square wave will produce a sine wave with a slower slew rate, this may hurt the jitter performance slightly Filtering the clock can eliminate clock related spurs, especially those associated with different frequencies coupling in due to clock isolation 23
Clocking with Sine Wave vs. Square Wave A square wave clock (e.g. LVPECL) has a very high slew rate, but does not allow clock filtering as clock harmonics generate the high slew rate Clock Slew Rate Harmonics Noise Frequency Filtering the clock removes clock noise, but limits the slew rate Slew Rate Bandpass Filter Lower Noise Frequency
Example: LMK04803 Filtering The plot below has two phase noise measurements overlaid from the same LMK04803, but the slightly darker trace has a relatively tight LC band-pass filter on it. Note that the overall jitter in the 1 kHz to 40 MHz bandwidth has actually degraded slightly for the filtered case due to a slower slew rate from filtering out the harmonics. Higher in-band phase noise However, the wideband noise has gone from -163 dBc/Hz to -174 dBc/Hz. Integrated over 500 MHz, this will make a significant difference (~200 fs) and will easily overcome the added jitter due to a lower slew rate. Lower wide-band noise 25
Example: ADS5483 w/ and w/o filtering Without Filter Clocking with a sine wave can reduce clock related spurs. With Filter 26
Clocking ADCs: Effect of Clock Slew Rate The jitter generated by the ADC clock receiver is affected by the clock slew rate Filtering the ADC clock will lower the clock slew rate by removing the harmonics A slower slew rate causes the receiver to be more susceptible to variations in the zero crossing point Receiver noise Aperture Jitter Total Jitter ~ (Clock Jitter2 + Receiver Jitter2 + Aperture Jitter2)1/2 Clock Jitter V/ t = slew rate Receiver Jitter ~ Receiver Noise * V/ t
Phase noise for slower slew rate For a clock that has ~9 dBm less power, jitter has been increased from 31.52 fs to 72.208 fs -3.35 dBm Clock: 6.11 dBm Clock: 28
A DIFFERENT WAY TO LOOK AT CLOCK JITTER/NOISE 29
Limitation of the Traditional SNR Calculation Due to Jitter The traditional SNR due to jitter equation gives the SNR over the entire Nyquist band, with the jitter measured over a wide clock offset frequency The equation is a function of the analog input frequency and jitter performance where = = 2 20 log( ) SNR dBc f j in j : f input frequency in = clock jitter j If the ADC clock is already fine tuned to the best jitter performance, would the only option left to meet the stringent SNR performance is to adjust the input frequency? If so, what is the point of over-sampling ADCs? 30
General Equation for ADC SNR It turns out the SNR equation is also a function of clock frequency as well. Recall the jitter equation: N 2 10 10 = j 2 f clk If we substitute the jitter equation into the SNR equation, we would get the following: 2 log( 20 in j f dBc SNR = N 2 10 f 10 ) 2 clk f N = 20 log( 2 10 ) in 10 f clk f N = 20 log( 2 10 ) 20 log( ) in 10 f clk f N = + 20 log( 2 10 ) 20 log( ) clk f 10 in The first term is the inherent integrated noise due to clock noise. The second term is a correction term. This is important to help us understand the performance of over-sampling. If over-sampling is used, the SNR can be improved 31
Why is the general equation important? The general equation is important because the traditional equation often simplifies the ADC clock noise floor as an uniform white noise. In reality, the ADC clock usually has better noise behavior as the offset frequency increases, and also, the clock is often well filtered. Simplified integrated clock noise Actual phase noise 32
System Requirement Implication Most importantly, some of the stringent system requirements often are bandwidth specific. I.e. noise spec over a specific bandwidth. For instance, when given a certain blocker signal, the traditional SNR calculation may overestimate the noise over the bandwidth of the wanted signal. This may make jitter specification of the clock impossible to achieve. 33
Experiment Result ADS4149 at 250MSPS Two inputs shown and overlaid: 10MHz and 100MHz Clocking the ADC with a 250MHz tone + 10MHz noise ranging from 240MHz to 250MHz (DAC5681 output) 34
ADC Test Result 20log(250/100) = 8dBc 20log(250/10) = 28dBc 35
SNR Jitter estimate is the same for DACs The total SNR is the vector sum of all individual SNR contributions 1 = 10 log SNR total SNR SNR SNR QUANT CLK THERM + + 10 10 10 10 10 10 SNRQUANT = SNR due to quantization SNRCLK = SNR due to clock and aperture jitter SNRTHERM = SNR due to thermal and transistor noise Similar treatment of clock jitter (integrated phase noise) for SNR limit of DAC sampled system where = = 2 20 log( ) SNR dBc f j if j : f output frequency if = clock jitter j 37
Is Jitter Applicable For DACs? For DACs, generally the noise spectral density (NSD) is more important than overall SNR The shape of the NSD around the carrier must meet mask requirements When SNR is required, customer s often limit the bandwidth of the transmitted signal by a bandpass or lowpass filter For this reason, newer datasheets report NSD rather than SNR fs = 1GSPS f out = 20MHz DAC output noise is comprised of Quantization noise Thermal noise Jitter noise Data dependent noise Signal Noise 38
Why NSD over SNR? In real systems, there is often tight filtering around the band of interest, where all the noise outside of that band is filtered out. Rather than showing the SNR of the signal in the first Nyquist zone, it is more convenient to show the noise power so that the total noise power in the unfiltered band can be readily calculated For example, consider a DAC3484 running at 1228.8 MSPS with a band of interest of 100 MHz and the following filters: A 614.4-MHz low-pass filter (passing full first Nyquist zone): ( dBc dBFS SNRdBFS 160 0 = ( ) ) + = / 10 log 614 4 . 72 12 . Hz MHz dBFS A 100-MHz low-pass filter: SNRdBFS = ( ( ) ) + = 0 160 / 10 log 100 80 dBFS dBc Hz MHz dBFS 39
Converting NSD to SNR The SNR of the DAC can be calculated from the NSD spec The SNR was traditionally defined as the ratio of the power of the fundamental to the power of the noise integrated over the first Nyquist zone. ( , l fundamenta dBm dBc NSD P SNR = ( ) 2 ) F + 10 log S / dBm Hz It can also be calculated directly in dBFS from the NSD in dBc/Hz ( 0 dBFS NSD dBFS SNR = ( ) 2 ) F + 10 log S / dBc Hz Example: DAC3484 running at 1.25 GSPS with 10 MHz output ( dBFS SNR dBFS 0 = ( ) ) . 1 25 GHz 2 + = 160 / 10 log 72 04 . dBc Hz dBFS 40
NSD to SNR tradeoffs Jitter/Phase noise SNR estimates based on Jitter are good estimates for SNR for the entire Nyquist band may be too pessimistic for BW limited applications. SNR estimates based on NSD (typically measured at some MHz offset) do not account for close-in phase noise which could affect inband EVM Useful for out of band estimates like ACPR Also useful for transmit mask requirements Using the clock NSD curve and BW limited noise calculations would be the ideal solution for in-band and out-of-band measurements.
CLK Phase Noise effects on sampled systems For both sampled systems of the ADC and DAC the CLK phase noise will be translated from the clock to the sampled outputs with the following relationship: f = _ _ _ 20 log clock NSD output clock in NSD f _ output signal All in-band (%EVM, RX sensitivity) and out-of-band (ACPR, TX Mask) measurements can be based on the measured phase noise plot of the ADC and DAC clock source Clock phase noise vs. DAC output phase noise -70 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 -80 983 04 . 14 dB 20 * log -90 200 Phase noise (dBc/Hz) -100 -110 -120 -130 -140 983.04MHz Clock phase noise 200MHz DAC output phase noise -150 -160
Intrinsic DAC noise effects At higher frequency offsets where the phase noise of the clock drops off, the intrinsic noise of the DAC will play a role in the overall noise floor of the output spectrum Measurements of the CLK NSD and the DAC output NSD show that there is some discrepancy between the estimates this is accounted for by the DAC intrinsic noise due to the Thermal/Device effects Predicted DAC output NSD vs. Measured DAC output NSD @1MHz frequency -140 10 100 1000 -145 -150 -155 -160 -165 -170 Predicted DAC output NSD -175 Measured DAC output NSD -180 -185 f _ DAC clock = + _ _ _ _ 20 log _ int _ DAC output NSD DAC clock NSD DAC rinsic noise f _ DAC output
Intrinsic DAC noise effects The Intrinsic DAC noise is frequency dependent and measured at a particular offset frequency will only be approximately accurate for other offset frequencies. Intrinsic Noise estimates made at 40MHz offset are somewhat accurate for NSD estimates at the same frequency offset using different clock sources. The intrinsic noise is due to quantization and thermal noise sources Error in all cases DAC intrinsic noise @40MHz -146 2 0 50 100 150 200 250 300 350 400 450 500 1ps_peaking 200fs_peaking 500fs_1MHz 500fs_peaking 1ps_1MHz 200fs_1MHz -148 1.5 DAC noise Error (dB) -150 1 -152 0.5 -154 0 0 50 100 150 200 250 300 350 400 450 500 -156 -0.5 -158 -1 -160 -1.5 -162 -2 DAC output frequency (MHz) DAC output frequency
EXAMPLES USING NSD FOR %EVM AND ACPR 45
DAC NSD Application measurement - EVM WCDMA signal 3.84MHz BW, IF=122.88M, Sample rate 983.04Msps, 1% EVM Assuming that %EVM is a measure of the SNR of the average inband signal power to the average inband NSD we can estimate the required average NSD of the clock (-105.84dBc/Hz avg at DAC output) NSD SNR 10*log(BW ) 40 10*log(3.84M ) 105.84 = = = Scale by IF and Sample rate (-87.78dBc/Hz avg at Clock source) 983.04 = + clock _NSD DAC_NSD 20*log122.88 = + 105.84 18.06 87.78 =
DAC NSD Application measurement - EVM Average Clock NSD within 3.84MHz around the fundamental clock frequency needs to be less than -87.78dBc/Hz The average clock NSD must be less than the predicted clock NSD to meet system requirements for EVM Phase noise Peaking NSD cause EVM fluctuation Predicted clock NSD Average in-band NSD @ clock determine EVM 1.92MHz Frequency shift
DAC NSD Application measurement - ACPR WCDMA signal 3.84MHz BW, IF=122.88M, Sample rate 983.04Msps, ACPR=70dB, Alt ACPR=75dBc The Clock NSD for both the ACPR and Alt ACPR is given by: Clock NSD ACPR = -118dBc/Hz, Clock NSD Alt ACPR = -123dBc/Hz 983.04 = + clock _NSD_5MHz DAC_NSD_ Adj 20*log122.88 = = NSD_ Adj ACPR_ Adj 10*log BW 70 10*log(3.84M ) 135.84 = = + 135.84 18.06 117.78 = 983.04 = + clock _NSD_10MHz DAC_NSD_ Alt 20*log122.88 = = NSD_ Alt ACPR_ Alt 75 10*log(3.84M ) 140.84 = 10*log BW = + 140.84 18.06 122.78 =
DAC NSD Application measurement - ACPR Using some common clock sources we can see that the Clock NSD at ACPR and Alt ACPR frequency offsets is well below these NSD numbers. Phase noise performance 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 -60.00 -80.00 Phase noise -100.00 -120.00 -140.00 -160.00 1ps_close_in 1ps_peaking 500fs_close_in 500fs_peaking 200fs_peaking 200fs_wide_band
DAC NSD Application measurement - ACPR Clock NSD at the ACPR and Alt ACPR offsets that there is negligible difference between using different clocks at different IF frequencies. Follows the shape of Intrinsic DAC noise. ACPR vs. different clocks -64 0 50 100 150 200 250 300 350 400 450 500 -66 -68 -70 ACPR -72 -74 best case 1ps peaking 500fs peaking 200fs peaking 1ps close-in 500fs close-in 200fs close-in -76 -78 -80 DAC output frequency
