Updates on HBU Integration at Heidelberg University
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KIP, Heidelberg University
Wei Shen
2018.09.19
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Status of the KLauS ASIC
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Temperature measurements
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Timing measurements
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The next KLauS version 6
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Status of the KLauS HBU integration
19.09.2018
Wei Shen, KLauS Update
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AD conversion @ fixed DC input
19.09.2018
Wei Shen, KLauS Update
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Differential Non-Linearity (ROI)
No big changes in ADC alone
.
Expected: performance determined by the
mismatches between capacitors
.
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Input SiPM bias
:
doesn‘t change
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Front-end Pedestal
:
no big change
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Charge injection
:
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For the working range 20-40°C, delta < 3 bin,
within 1% FSR.
19.09.2018
Wei Shen, KLauS Update
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Close look at fixed charge injection with
pulse reconstruction
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Hold-delay contributes: 0.4ns/
°
C
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Peak time no changes, but peak height changes
around 1bin/
°
C
19.09.2018
Wei Shen, KLauS Update
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Fixed gDAC and fDAC
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19.09.2018
Wei Shen, KLauS Update
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17.04.2018
Zhenxiong, KLauS CTR
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KLauS5
Hamamatsu MPPC S12643-050CN(X)
Energy resolution:
11.5%
Two peaks (511k
eV, 1275keV
) are used to
do the calibration
Two ASIC used. Scope to get the amplitude/timing information
Same as EndoToFPET setup with STiC3
Energy measuremets with
KLauS internal ADC
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17.04.2018
Zhenxiong, KLauS CTR
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Re-measure
the power consumption under
acquisition-off state
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Same setup as before
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Setup calibrated: resistor, gain, offset
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Exclude power from other active components
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Results:
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Same for results under acquisition-on state
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2.5 mW/Ch
(VA3.3
0.93, VA1.8
1.53
)
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New results for acquisition-off state
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Power-consumption under 0.5% PP duty-cycle:
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20 uW/Ch
(for analog power only)
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5 uW/Ch budget left for TDC and digital parts (challenging)
28.08.2018
Zhenxiong, KLauS HBU & TDC
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TDC Design Specfications:
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Bin-size: 200ps
(depending on the actual power consumption)
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Time range: 16ms
for test-beam mode (1.6ms for ILC mode)
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Fast lock time: < 10us
(smaller than the front-end settling time)
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Power consumption: < 18mW
(for all channels, scaled to
2.5uW/Ch
with 0.5% duty cycle)
•
Design Implementations:
•
Data structure:
BXID + CC(16bits, 1.6ms) + FC(7bits, 25ns)
•
Byte number of hit data 5 bytes unchanged; T0 channel store
s
the BXID
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Discard the T0 channel data if no event hit
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TDC strucutre: PLL-based TDC, PLL clock multiply factor of 4, slightly different from STiC
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The KLauS6 will be submitted at Q1 2019
28.08.2018
Zhenxiong, KLauS HBU & TDC
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KLauS5 packaging
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52 naked chips will be sent and expect get 47 chips back
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Purchase Order from DESY received by Novapack
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Expected submit the substrate order before the end of this month (guess it‘s delayed)
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Expected get the packaged chip by the end of Oct.
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Test-board for the packaged chip
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Design on-going, expected ready by the end of Oct.
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HBU integration
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HBU_HD Schematic design already finished by M
athias. Waiting for the PCB layout design......
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Also POWER board finished
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Firmware and software design will start once we get the HBU board ready
19.09.2018
Wei Shen, KLauS Update
11
In this series of updates by Wei Shen, the KLauS ASIC temperature and timing measurements are discussed, along with the progress of the HBU integration at Heidelberg University. Details on ADC performance, charge injection, timing measurements, and CTR measurement setup are provided, offering insights into the advancements made in the project.
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Presentation Transcript
KLauS: Updates on HBU Integration KLauS: Updates on HBU Integration KIP, Heidelberg University Wei Shen 2018.09.19
Overview Overview Status of the KLauS ASIC Temperature measurements Timing measurements The next KLauS version 6 Status of the KLauS HBU integration 19.09.2018 Wei Shen, KLauS Update 2
ADC @ different temperature ADC @ different temperature AD conversion @ fixed DC input Differential Non-Linearity (ROI) No big changes in ADC alone. Expected: performance determined by the mismatches between capacitors. 19.09.2018 Wei Shen, KLauS Update 3
Fullchain charge injection @ different temperature Fullchain charge injection @ different temperature Input SiPM bias: doesn t change Front-end Pedestal: no big change Charge injection: For the working range 20-40 C, delta < 3 bin, within 1% FSR. 19.09.2018 Wei Shen, KLauS Update 4
Fullchain @ fixed charge injection Fullchain @ fixed charge injection Close look at fixed charge injection with pulse reconstruction Hold-delay contributes: 0.4ns/ C Peak time no changes, but peak height changes around 1bin/ C Fixed gDAC and fDAC 19.09.2018 Wei Shen, KLauS Update 5
Timing measurements Timing measurements Time walk and rising edge jitter of the front-end trigger signal Jitter around 50-100ps( ) for the front-end No reason to pursue a TDC with binsize smaller than 180ps(50 12) 19.09.2018 Wei Shen, KLauS Update 6
CTR Measurement Setup CTR Measurement Setup Scintillator: LYSO:Ce, 3.1 3.1 15??2 Energy resolution: 11.5% Hamamatsu MPPC S12643-050CN(X) Two peaks (511keV, 1275keV) are used to do the calibration Temperature: 15 Two ASIC used. Scope to get the amplitude/timing information Energy measuremets with KLauS internal ADC KLauS5 Same as EndoToFPET setup with STiC3 17.04.2018 Zhenxiong, KLauS CTR 7
Coincidence Timing Resolution Coincidence Timing Resolution Results (no needs to apply time-walk correction): 393ps (FWHM) with energy cut of ? 423ps (FWHM) with energy cut of 2? 17.04.2018 Zhenxiong, KLauS CTR 8
TDC Design Considerations: power constraints TDC Design Considerations: power constraints Re-measure the power consumption under acquisition-off state Same setup as before Setup calibrated: resistor, gain, offset Exclude power from other active components Results: Same for results under acquisition-on state 2.5 mW/Ch (VA3.3 0.93, VA1.8 1.53 ) New results for acquisition-off state Power-consumption under 0.5% PP duty-cycle: 20 uW/Ch (for analog power only) 5 uW/Ch budget left for TDC and digital parts (challenging) 28.08.2018 Zhenxiong, KLauS HBU & TDC 9
KLauS6 Design Status KLauS6 Design Status TDC Design Specfications: Bin-size: 200ps(depending on the actual power consumption) Time range: 16ms for test-beam mode (1.6ms for ILC mode) Fast lock time: < 10us (smaller than the front-end settling time) Power consumption: < 18mW (for all channels, scaled to 2.5uW/Ch with 0.5% duty cycle) Design Implementations: Data structure: BXID + CC(16bits, 1.6ms) + FC(7bits, 25ns) Byte number of hit data 5 bytes unchanged; T0 channel stores the BXID Discard the T0 channel data if no event hit TDC strucutre: PLL-based TDC, PLL clock multiply factor of 4, slightly different from STiC The KLauS6 will be submitted at Q1 2019 28.08.2018 Zhenxiong, KLauS HBU & TDC 10
Updates on the HBU integration Updates on the HBU integration KLauS5 packaging 52 naked chips will be sent and expect get 47 chips back Purchase Order from DESY received by Novapack Expected submit the substrate order before the end of this month (guess it s delayed) Expected get the packaged chip by the end of Oct. Test-board for the packaged chip Design on-going, expected ready by the end of Oct. HBU integration HBU_HD Schematic design already finished by Mathias. Waiting for the PCB layout design...... Also POWER board finished Firmware and software design will start once we get the HBU board ready 19.09.2018 Wei Shen, KLauS Update 11
