Timers and Interrupts in Operating Systems

 
Timers and Interrupts
 
Marion Sudvarg, David Ferry, Chris Gill, Brian Kocoloski
CSE 522S – Advanced Operating Systems
Washington University in St. Louis
St. Louis, MO 63143
 
1
Preemptive Multitasking
 
Last Time
: CFS and CPU cgroups
These mechanisms decide which, and for how
long, a process can run
But, how does the kernel stop a process?
A system call switches execution context into the
kernel – but this is not sufficient
What about a process that never (1) voluntarily
yields the CPU or (2) makes a syscall?
Must be somehow preempted to support
multitasking!
2
CSE 522S – Advanced Operating Systems
 
CSE 422S Review: Timer Interrupts
 
Hardware supports periodically-timed
preemption of processes by the kernel
System timer: fires at known periodic intervals
Allows the kernel to say to the CPU: stop the
currently running process and let 
me
 run after
some period of time has expired
 
Kernel programs 
timer interrupts
 to fire at
known points in the future
E.g.,
 program the system timer to always
interrupt the processor every 10 ms
 
3
 
CSE 522S – Advanced Operating Systems
 
CSE 422S Review: Timer interrupts
 
4
 
./test
 
User space
 
Kernel space
 
CPU core
(executing instructions)
 
Timer
(hardware that supports
delivery of 
interrupts
)
 
CSE 522S – Advanced Operating Systems
 
CSE 422S Review: Timer interrupts
 
5
 
./test
 
User space
 
Kernel space
 
CPU core
(executing instructions)
 
Timer
(hardware that supports
delivery of 
interrupts
)
 
./test
 
CSE 522S – Advanced Operating Systems
 
CSE 422S Review: Timer interrupts
 
6
 
./test
 
User space
 
Kernel space
 
CPU core
(executing instructions)
 
Timer
(hardware that supports
delivery of 
interrupts
)
 
./test
 
Interrupt!
 
CSE 522S – Advanced Operating Systems
 
CSE 422S Review: Timer interrupts
 
7
 
./test
 
User space
 
Kernel space
 
Timer
interrupt
 
CPU core
(executing instructions)
 
Timer
(hardware that supports
delivery of 
interrupts
)
 
./test
 
Interrupt!
 
Interrupt forces the CPU to enter kernel mode where
a special function called the 
timer interrupt
 will execute
 
CSE 522S – Advanced Operating Systems
 
CSE 422S Review: Timer interrupts
 
8
 
./test
 
User space
 
Kernel space
 
Timer
interrupt
 
CPU core
(executing instructions)
 
Timer
(hardware that supports
delivery of 
interrupts
)
 
./test
 
Interrupt!
 
Interrupt forces the CPU to enter kernel mode where
a special function called the 
timer interrupt
 will execute
 
CSE 522S – Advanced Operating Systems
 
CSE 422S Review: Timer interrupts
 
9
 
./test
 
User space
 
Kernel space
 
Timer
interrupt
 
Timer
interrupt
 
Timer
interrupt
 
CSE 522S – Advanced Operating Systems
 
Timer Hardware
 
Programmable Interval Timer (PIT)
Has 3 programmable counter registers
Each register counts down at a constant rate
When a register reaches 0, it sends an interrupt
 
High Precision Event Timer (HPET)
Similar to PIT
More complex logic, allows finer-grained control
 
Advanced Programmable Interrupt Controller (APIC)
For Intel x86 hardware
Can be set to TSC-Deadline mode
Generates an IRQ when the TSC (timestamp counter) reaches programmed deadline
 
BCM System Timer
Raspberry Pi board system timer
Has a single constant-rate counter
4 programmable registers send unique interrupts when they match the timer
 
ARM PMU
Can be programmed to generate interrupts when a counter overflows
Set counter to (OVERFLOW – COUNT) to receive interrupt when COUNT is reached
 
10
 
CSE 522S – Advanced Operating Systems
 
Questions
 
How can timer interrupts be used to
determine an absolute, real-world
measurement of time?
 
How can timer interrupts be used to
implement arbitrary user timers?
(e.g., when user executes 
sleep(5)
)
 
11
 
CSE 522S – Advanced Operating Systems
Types of Timers
12
CSE 522S – Advanced Operating Systems
 
Relative
 
vs 
Absolute
Set a timer for 2
seconds from now
sleep(2)
Set an alarm at
5:29:31
 
Periodic
Set a timer to go off
every 10ms
(kernel timer interrupt)
(poll a sensor)
Timer Implementation
How are they implemented “under the hood”?
13
CSE 522S – Advanced Operating Systems
Timeout
Priority Queue
Timer
CPU
Core
 
Insert Absolute
Timeout
 
Register Next
Timeout
 
Time Elapses
 
Interrupt!
 
Signal
Periodic Timer Implementation
14
CSE 522S – Advanced Operating Systems
timer(10ms,PERIODIC)
Hardware
timer(10ms,PERIODIC)
Hardware
 
set(now + 10ms)
 
signal
 
10 ms
timer(10ms,PERIODIC)
Hardware
timer(10ms,PERIODIC)
Hardware
 
set(now + 10ms)
 
signal
 
10 ms
 
What’s the problem?
 
10 ms
 
10 ms
 
??
 
>20 ms
 
Timer Drift
Correct Implementation
15
CSE 522S – Advanced Operating Systems
timer(10ms,PERIODIC)
Hardware
timer(10ms,PERIODIC)
Hardware
 
timeout += 10ms
set(timeout)
 
Signal
 
10 ms
 
10 ms
 
10 ms
 
INIT: timeout = now
timer(10ms,PERIODIC)
Hardware
timer(10ms,PERIODIC)
Hardware
 
timeout += 10ms
set(timeout)
 
Signal
 
10 ms
 
20 ms
 
Other Interrupts
 
So far we’ve discussed timer interrupts
 
Other devices generate interrupts too:
Keyboard/Mouse
Network Card: “Packets available!”
Hard Drive: “Disk read complete!”
Sensors in Cyber-Physical Systems: “Tolerance
limit exceeded!”
 
16
 
CSE 522S – Advanced Operating Systems
ARM Interrupt Overview
17
CSE 522S – Advanced Operating Systems
Generic Interrupt Controller (GIC)
CPU
 
FIQ
:
ARM-specific
Fast-path for single interrupt source
Removes overhead of source lookup
Has own bank of registers
Eliminates context switch overhead
nIRQ
Timers
External Interrupt Sources
 
Interrupt lines are numbered
IRQ sent with line # to CPU
CPU jumps to interrupt table, looks up line number
(similar concept to software traps, syscalls)
Lines typically edge-triggered – CPU must clear line
to receive new interrupts on that line
Caution
: Multiple devices might share a line!
 
Today’s Readings
 
LKD Chapter 7
: Coverage of hardware interrupts and
handlers
LKD Pages 216-220
: Read the “Hardware Clocks and
Timers” and “The Timer Interrupt Handler” sections
LKD Pages 222-224
: An overview of timers
LSP Chapter 11
: An overview of time and timer
mechanisms provided to userspace
(Optional) 
LPI Chapter 23
: An in-depth reference for
userspace time APIs
(Optional) 
Linux Device Drivers Chapter 10
: In-depth
description of interrupt handling from a driver developer’s
perspective, free PDF linked from website
 
18
 
CSE 522S – Advanced Operating Systems
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This content discusses the importance of timers and interrupts in operating systems, focusing on how they facilitate preemptive multitasking. It covers how hardware timer interrupts help in preemption of processes by the kernel, ensuring efficient task scheduling and resource management in modern operating systems.

  • Operating Systems
  • Timers
  • Interrupts
  • Preemptive Multitasking
  • Process Scheduling

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  1. Timers and Interrupts Marion Sudvarg, David Ferry, Chris Gill, Brian Kocoloski CSE 522S Advanced Operating Systems Washington University in St. Louis St. Louis, MO 63143 1

  2. Preemptive Multitasking Last Time: CFS and CPU cgroups These mechanisms decide which, and for how long, a process can run But, how does the kernel stop a process? A system call switches execution context into the kernel but this is not sufficient What about a process that never (1) voluntarily yields the CPU or (2) makes a syscall? Must be somehow preempted to support multitasking! CSE 522S Advanced Operating Systems 2

  3. CSE 422S Review: Timer Interrupts Hardware supports periodically-timed preemption of processes by the kernel System timer: fires at known periodic intervals Allows the kernel to say to the CPU: stop the currently running process and let me run after some period of time has expired Kernel programs timer interrupts to fire at known points in the future E.g., program the system timer to always interrupt the processor every 10 ms 3 CSE 522S Advanced Operating Systems

  4. CSE 422S Review: Timer interrupts ./test CPU core (executing instructions) User space Kernel space Timer (hardware that supports delivery of interrupts) 4 CSE 522S Advanced Operating Systems

  5. CSE 422S Review: Timer interrupts ./test ./test CPU core (executing instructions) User space Kernel space Timer (hardware that supports delivery of interrupts) 5 CSE 522S Advanced Operating Systems

  6. CSE 422S Review: Timer interrupts ./test ./test Interrupt! CPU core (executing instructions) User space Kernel space Timer (hardware that supports delivery of interrupts) 6 CSE 522S Advanced Operating Systems

  7. CSE 422S Review: Timer interrupts ./test ./test Interrupt! CPU core (executing instructions) User space Kernel space Timer Timer interrupt (hardware that supports delivery of interrupts) Interrupt forces the CPU to enter kernel mode where a special function called the timer interrupt will execute 7 CSE 522S Advanced Operating Systems

  8. CSE 422S Review: Timer interrupts ./test ./test Interrupt! CPU core (executing instructions) User space Kernel space Timer Timer interrupt (hardware that supports delivery of interrupts) Interrupt forces the CPU to enter kernel mode where a special function called the timer interrupt will execute 8 CSE 522S Advanced Operating Systems

  9. CSE 422S Review: Timer interrupts ./test User space Kernel space Timer interrupt Timer interrupt Timer interrupt 9 CSE 522S Advanced Operating Systems

  10. Timer Hardware Programmable Interval Timer (PIT) Has 3 programmable counter registers Each register counts down at a constant rate When a register reaches 0, it sends an interrupt High Precision Event Timer (HPET) Similar to PIT More complex logic, allows finer-grained control Advanced Programmable Interrupt Controller (APIC) For Intel x86 hardware Can be set to TSC-Deadline mode Generates an IRQ when the TSC (timestamp counter) reaches programmed deadline BCM System Timer Raspberry Pi board system timer Has a single constant-rate counter 4 programmable registers send unique interrupts when they match the timer ARM PMU Can be programmed to generate interrupts when a counter overflows Set counter to (OVERFLOW COUNT) to receive interrupt when COUNT is reached 10 CSE 522S Advanced Operating Systems

  11. Questions How can timer interrupts be used to determine an absolute, real-world measurement of time? How can timer interrupts be used to implement arbitrary user timers? (e.g., when user executes sleep(5)) 11 CSE 522S Advanced Operating Systems

  12. Types of Timers Relativevs Absolute Set a timer for 2 seconds from now sleep(2) Set an alarm at 5:29:31 Periodic Set a timer to go off every 10ms (kernel timer interrupt) (poll a sensor) CSE 522S Advanced Operating Systems 12

  13. Timer Implementation How are they implemented under the hood ? Timer Hardware Timeout Priority Queue Timer Insert Absolute Timeout Register Next Timeout Time Elapses Timer Hardware CPU Core Interrupt! 13 CSE 522S Advanced Operating Systems

  14. Periodic Timer Implementation What s the problem? set(now + 10ms) timer(10ms,PERIODIC) Hardware 10 ms 10 ms signal timer(10ms,PERIODIC) Hardware >20 ms ?? set(now + 10ms) timer(10ms,PERIODIC) Hardware Timer Drift 10 ms 10 ms signal timer(10ms,PERIODIC) Hardware CSE 522S Advanced Operating Systems 14

  15. Correct Implementation INIT: timeout = now timeout += 10ms set(timeout) timer(10ms,PERIODIC) Hardware 10 ms 10 ms Signal timer(10ms,PERIODIC) Hardware 20 ms timeout += 10ms set(timeout) timer(10ms,PERIODIC) Hardware 10 ms 10 ms Signal timer(10ms,PERIODIC) Hardware CSE 522S Advanced Operating Systems 15

  16. Other Interrupts So far we ve discussed timer interrupts Other devices generate interrupts too: Keyboard/Mouse Network Card: Packets available! Hard Drive: Disk read complete! Sensors in Cyber-Physical Systems: Tolerance limit exceeded! CSE 522S Advanced Operating Systems 16

  17. ARM Interrupt Overview Interrupt lines are numbered IRQ sent with line # to CPU CPU jumps to interrupt table, looks up line number (similar concept to software traps, syscalls) Lines typically edge-triggered CPU must clear line to receive new interrupts on that line Caution: Multiple devices might share a line! External Interrupt Sources Generic Interrupt Controller (GIC) nIRQ FIQ: ARM-specific Fast-path for single interrupt source Removes overhead of source lookup Has own bank of registers Eliminates context switch overhead Timers CPU CSE 522S Advanced Operating Systems 17

  18. Todays Readings LKD Chapter 7: Coverage of hardware interrupts and handlers LKD Pages 216-220: Read the Hardware Clocks and Timers and The Timer Interrupt Handler sections LKD Pages 222-224: An overview of timers LSP Chapter 11: An overview of time and timer mechanisms provided to userspace (Optional) LPI Chapter 23: An in-depth reference for userspace time APIs (Optional) Linux Device Drivers Chapter 10: In-depth description of interrupt handling from a driver developer s perspective, free PDF linked from website CSE 522S Advanced Operating Systems 18

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