Interrupts in Computer Systems
1
COMP541
COMP541
Interrupts, DMA, Serial I/O
Interrupts, DMA, Serial I/O
Montek Singh
Montek Singh
Nov 19, 2014
Nov 19, 2014
2
Interrupts
Two main kinds
Two main kinds
Internal
Internal
Error when executing an instruction
Error when executing an instruction
Floating point exception
Floating point exception
Virtual memory page fault
Virtual memory page fault
Trying to access protected memory
Trying to access protected memory
Invalid opcode!
Invalid opcode!
System call requested by software
System call requested by software
To request OS services
To request OS services
External
External
I/O
I/O
3
Internal
More complicated because two possible actions
More complicated because two possible actions
may abort instruction
may abort instruction
access to protected memory not allowed
access to protected memory not allowed
or, OS corrects the situation and restarts instruction
or, OS corrects the situation and restarts instruction
e.g., virtual memory page fault
e.g., virtual memory page fault
Question:
Question:
What happens for arithmetic overflow/divide-by-0?
What happens for arithmetic overflow/divide-by-0?
4
When Interrupt Occurs
Interrupt enable register
Interrupt enable register
Sometimes levels of interrupts individually enabled/disabled
Sometimes levels of interrupts individually enabled/disabled
PC is changed to new location
PC is changed to new location
One or more interrupt locations stored
One or more interrupt locations stored
“
“
vectored interrupts
vectored interrupts
”
”
Or a fixed location
Or a fixed location
example: MIPS (e.g., 0xC000 0000)
example: MIPS (e.g., 0xC000 0000)
Old PC saved to register or stack
Old PC saved to register or stack
Many machines have stack pointer
Many machines have stack pointer
5
Registers
Sometimes registers saved by
Sometimes registers saved by
hardware
hardware
Some machines have one or more sets of registers
Some machines have one or more sets of registers
Often: software must save registers
Often: software must save registers
Push them onto stack
Push them onto stack
Return from interrupt
Return from interrupt
Some CPUs provide a special instruction to return from
Some CPUs provide a special instruction to return from
interrupt
interrupt
“
“
rfi
rfi
”
”
or
or
“
“
iret
iret
”
”
Others use the standard procedure return instruction
Others use the standard procedure return instruction
jr, ret, etc.
jr, ret, etc.
Restore registers before returning
Restore registers before returning
6
Cause of Interrupt
Need way to determine what caused interrupt
Need way to determine what caused interrupt
Note it can be more than one thing
Note it can be more than one thing
Vectored Interrupts
Vectored Interrupts
Different types cause branches to different locations
Different types cause branches to different locations
Sometimes prioritized
Sometimes prioritized
Register to store cause
Register to store cause
“Cause” register
“Cause” register
7
Supervisory Mode
Modern computers have user mode and one or more
Modern computers have user mode and one or more
“supervisory modes”
“supervisory modes”
User mode restricted
User mode restricted
Can
Can
’
’
t write to many system registers, such as interrupt
t write to many system registers, such as interrupt
enable
enable
Can
Can
’
’
t write to some parts of memory
t write to some parts of memory
Usually I/O restricted
Usually I/O restricted
Interrupts cause switch to supervisory mode
Interrupts cause switch to supervisory mode
In this mode, software has access to several privileged parts
In this mode, software has access to several privileged parts
of the system
of the system
e.g.: kernel memory, IE register, etc.
e.g.: kernel memory, IE register, etc.
Question: Which interrupts?
Question: Which interrupts?
Some Interrupt Hardware
An example
An example
implementation
implementation
Interrupts ORed
Interrupts ORed
Response if IE and at end
Response if IE and at end
of instruction
of instruction
Ack interrupt
Ack interrupt
Vector address to PC
Vector address to PC
new PC calculated using the
new PC calculated using the
interrupt number
interrupt number
e.g.,
e.g.,
IntNum * a + b
IntNum * a + b
Save current PC on stack
Save current PC on stack
to return
to return
8
9
Return from interrupt
Very similar to return from procedure
Very similar to return from procedure
Some additional actions
Some additional actions
PSR holds IE bit
PSR holds IE bit
Restoring PSR turns interrupts on
Restoring PSR turns interrupts on
Exception (from Patterson Hennessey, multicycle MIPS)
MIPS has a simpler impl.
10
Branch to
fixed addr
Undefined instruction and arithmetic overflow
11
Restarting Instruction?
Imagine the interrupt (exception) was a page fault
Imagine the interrupt (exception) was a page fault
Need to get the page, and then
Need to get the page, and then
rerun
rerun
the instruction
the instruction
Hence: subtract 4 from PCPlus4, so this instruction is redone
Hence: subtract 4 from PCPlus4, so this instruction is redone
Keeping instructions simple/short helps out!
Keeping instructions simple/short helps out!
Otherwise may need to save some intermediate state
Otherwise may need to save some intermediate state
Imagine block-move instruction such as the Pentium MOVS
Imagine block-move instruction such as the Pentium MOVS
–
moves/copies an entire string (of variable length) in a single
moves/copies an entire string (of variable length) in a single
instruction!
instruction!
Types of I/O
Types of I/O
Programmed I/O
Programmed I/O
Direct Memory Access (DMA)
Direct Memory Access (DMA)
12
13
Direct Memory Access (DMA)
Programmed I/O
Programmed I/O
is when CPU reads/writes every
is when CPU reads/writes every
word
word
Specific instructions included for I/O, e.g.:
Specific instructions included for I/O, e.g.:
in 0xff00
in 0xff00
out 0xffe0
out 0xffe0
Problem: overhead is high; nothing else getting done on CPU
Problem: overhead is high; nothing else getting done on CPU
Especially for mass-storage devices like disk
Especially for mass-storage devices like disk
DMA: Let device controller read/write mem directly
DMA: Let device controller read/write mem directly
CPU goes about its usual business of executing other
CPU goes about its usual business of executing other
instructions
instructions
delegates the reading/writing to DMA controller
delegates the reading/writing to DMA controller
typically cannot access memory while DMA is going on!
typically cannot access memory while DMA is going on!
14
DMA Protocol
DMA protocol
DMA protocol
DMA device takes over main bus
DMA device takes over main bus
Becomes
Becomes
bus master
bus master
Asserts addresses
Asserts addresses
Basically interfaces to memory or memory controller
Basically interfaces to memory or memory controller
How?
DMA device requests bus (assert BR)
DMA device requests bus (assert BR)
CPU grants request (assert BG)
CPU grants request (assert BG)
CPU takes its signals to Hi-Z
CPU takes its signals to Hi-Z
now DMA can use its signals to connect with memory
now DMA can use its signals to connect with memory
no conflict with CPU’s signals (they are floating)
no conflict with CPU’s signals (they are floating)
15
Transfer Modes
Several types of transfer modes
Continuous
: DMA controller transfers all data (say a disk
sector) at once
As many memory cycles as data
Burst
: DMA controller cycle steals, takes a cycle at end of
every CPU instruction
Note: today’s processors are more sophisticated
there is a memory controller (“Northbridge”)
sits in-between CPU and memory
Why? Memories are more complex, caches, etc.
16
16
17
End of DMA
Controller needs to inform CPU
Controller needs to inform CPU
De-assert BR
De-assert BR
Then CPU lowers BG and proceeds
Then CPU lowers BG and proceeds
18
DMA Controller
Needs typical I/O signals
Needs typical I/O signals
Interrupt request
Interrupt request
Status of device
Status of device
Also needs controls for DMA transfer
Also needs controls for DMA transfer
Memory address
Memory address
Word count
Word count
19
Block Diagram
20
Typical Driver Interface
Software drivers
Software drivers
Set the memory address
Set the memory address
Set word count
Set word count
Assert “GO” (usually bit in control word)
Assert “GO” (usually bit in control word)
DMA controller starts copying …
DMA controller starts copying …
… and requests interrupt when transfer complete
… and requests interrupt when transfer complete
Trends in Communications
Older bus standards, such as ISA and PCI, were
parallel (conventional
“
bus
”
)
Newer (PCI Express) use serial channels (lanes)
So slots for slower devices can be x1
Slots for devices such as GPUs can be x16 (max x32 in spec)
1
6
l
a
n
e
P
C
I
-
E
(
b
e
l
o
w
)
1
l
a
n
e
(
r
i
g
h
t
)
Disks
Change from ATA/IDE to SATA
IDE had 16 data channels
SATA has 2 twisted pair (xmit and recv)
23
RS-232/UART
Called
Called
“
“
Asynchronous
Asynchronous
”
”
But both sides have precise clocks
But both sides have precise clocks
Agree on speed
Agree on speed
Receiver syncs during start bit
Receiver syncs during start bit
24
USB
One master
One master
The PC
The PC
Idea was to have thin
Idea was to have thin
cables and plug and
cables and plug and
play
play
Specs include hardware
Specs include hardware
and software
and software
We only cover hardware
We only cover hardware
25
USB – Packet serial I/O
Four wires total
Four wires total
+5v and GND
+5v and GND
Two signal wires
Two signal wires
Twisted pair
Twisted pair
Differential signaling
Differential signaling
Differential 1 is D+ > 2.8v and D- < 0.3v
Differential 1 is D+ > 2.8v and D- < 0.3v
Differential 0 is opposite
Differential 0 is opposite
Also a single-ended zero when D+ & D- low (end of packet,
Also a single-ended zero when D+ & D- low (end of packet,
reset, disconnect)
reset, disconnect)
26
Speed
Three speeds
Three speeds
High is 480 Mb/s (USB 2.0)
High is 480 Mb/s (USB 2.0)
Full is 12 Mb/s (USB 1.1)
Full is 12 Mb/s (USB 1.1)
Low is 1.5 Mb/s (USB 1.0)
Low is 1.5 Mb/s (USB 1.0)
New Super Speed, 5Gb/s!! (USB 3.0)
New Super Speed, 5Gb/s!! (USB 3.0)
High speed starts as full, then handshakes
High speed starts as full, then handshakes
and transitions
and transitions
High and low speeds interpret zeros and
High and low speeds interpret zeros and
ones inverted
ones inverted
27
Coding
NRZI
NRZI
Non-Return to Zero Inverted
Non-Return to Zero Inverted
Transition if sending 0, none if sending 1
Transition if sending 0, none if sending 1
Bit stuffing
Bit stuffing
Since a string of 1s causes no transitions, synchronization
Since a string of 1s causes no transitions, synchronization
may be lost
may be lost
A zero is stuffed in after six consecutive ones
A zero is stuffed in after six consecutive ones
Sync field
Sync field
Each packet starts with a sync
Each packet starts with a sync
8 bits: 00000001
8 bits: 00000001
28
Packets
Won
Won
’
’
t go into
t go into
details
details
Summary
Many types of I/O
memory-mapped is most common
different devices given different address ranges
many different device protocols
PS/2: keyboard, mice
RS-232: serial ports
USB: most common today
also Firewire, Thunderbolt, …
ethernet
also monitors, displays
we did VGA (other higher resolutions also possible)
DVI is most common today
29
Interrupts in computer systems play a crucial role in handling various events and managing the flow of instructions. This content discusses the types of interrupts, causes, handling procedures, and the role of supervisory modes in modern computers. It covers topics such as internal and external interrupts, register management during interrupts, interrupt handling procedures, and the transition to supervisory mode for privileged access. Additionally, it addresses common scenarios such as arithmetic overflow and divide-by-zero errors.
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Presentation Transcript
COMP541 Interrupts, DMA, Serial I/O Montek Singh Nov 19, 2014 1
Interrupts Two main kinds Internal Error when executing an instruction Floating point exception Virtual memory page fault Trying to access protected memory Invalid opcode! System call requested by software To request OS services External I/O 2
Internal More complicated because two possible actions may abort instruction access to protected memory not allowed or, OS corrects the situation and restarts instruction e.g., virtual memory page fault Question: What happens for arithmetic overflow/divide-by-0? 3
When Interrupt Occurs Interrupt enable register Sometimes levels of interrupts individually enabled/disabled PC is changed to new location One or more interrupt locations stored vectored interrupts Or a fixed location example: MIPS (e.g., 0xC000 0000) Old PC saved to register or stack Many machines have stack pointer 4
Registers Sometimes registers saved by hardware Some machines have one or more sets of registers Often: software must save registers Push them onto stack Return from interrupt Some CPUs provide a special instruction to return from interrupt rfi or iret Others use the standard procedure return instruction jr, ret, etc. Restore registers before returning 5
Cause of Interrupt Need way to determine what caused interrupt Note it can be more than one thing Vectored Interrupts Different types cause branches to different locations Sometimes prioritized Register to store cause Cause register 6
Supervisory Mode Modern computers have user mode and one or more supervisory modes User mode restricted Can t write to many system registers, such as interrupt enable Can t write to some parts of memory Usually I/O restricted Interrupts cause switch to supervisory mode In this mode, software has access to several privileged parts of the system e.g.: kernel memory, IE register, etc. Question: Which interrupts? 7
Some Interrupt Hardware An example implementation Interrupts ORed Response if IE and at end of instruction Ack interrupt Vector address to PC new PC calculated using the interrupt number e.g., IntNum * a + b Save current PC on stack to return 8
Return from interrupt Very similar to return from procedure Some additional actions PSR holds IE bit Restoring PSR turns interrupts on 9
Exception (from Patterson Hennessey, multicycle MIPS) MIPS has a simpler impl. Branch to fixed addr PC 4 stored Just two causes Undefined instruction and arithmetic overflow 10
Restarting Instruction? Imagine the interrupt (exception) was a page fault Need to get the page, and then rerun the instruction Hence: subtract 4 from PCPlus4, so this instruction is redone Keeping instructions simple/short helps out! Otherwise may need to save some intermediate state Imagine block-move instruction such as the Pentium MOVS moves/copies an entire string (of variable length) in a single instruction! 11
Types of I/O Programmed I/O Direct Memory Access (DMA) 12
Direct Memory Access (DMA) Programmed I/O is when CPU reads/writes every word Specific instructions included for I/O, e.g.: in 0xff00 out 0xffe0 Problem: overhead is high; nothing else getting done on CPU Especially for mass-storage devices like disk DMA: Let device controller read/write mem directly CPU goes about its usual business of executing other instructions delegates the reading/writing to DMA controller typically cannot access memory while DMA is going on! 13
DMA Protocol DMA protocol DMA device takes over main bus Becomes bus master Asserts addresses Basically interfaces to memory or memory controller 14
How? DMA device requests bus (assert BR) CPU grants request (assert BG) CPU takes its signals to Hi-Z now DMA can use its signals to connect with memory no conflict with CPU s signals (they are floating) 15
Transfer Modes Several types of transfer modes Continuous: DMA controller transfers all data (say a disk sector) at once As many memory cycles as data Burst: DMA controller cycle steals, takes a cycle at end of every CPU instruction Note: today s processors are more sophisticated there is a memory controller ( Northbridge ) sits in-between CPU and memory Why? Memories are more complex, caches, etc. 1
End of DMA Controller needs to inform CPU De-assert BR Then CPU lowers BG and proceeds 17
DMA Controller Needs typical I/O signals Interrupt request Status of device Also needs controls for DMA transfer Memory address Word count 18
Typical Driver Interface Software drivers Set the memory address Set word count Assert GO (usually bit in control word) DMA controller starts copying and requests interrupt when transfer complete 20
Trends in Communications Older bus standards, such as ISA and PCI, were parallel (conventional bus ) Newer (PCI Express) use serial channels (lanes) So slots for slower devices can be x1 Slots for devices such as GPUs can be x16 (max x32 in spec) 16 lane PCI-E (below) 1 lane (right)
Disks Change from ATA/IDE to SATA IDE had 16 data channels SATA has 2 twisted pair (xmit and recv)
RS-232/UART Called Asynchronous But both sides have precise clocks Agree on speed Receiver syncs during start bit 23
USB One master The PC Idea was to have thin cables and plug and play Specs include hardware and software We only cover hardware 24
USB Packet serial I/O Four wires total +5v and GND Two signal wires Twisted pair Differential signaling Differential 1 is D+ > 2.8v and D- < 0.3v Differential 0 is opposite Also a single-ended zero when D+ & D- low (end of packet, reset, disconnect) 25
Speed Three speeds High is 480 Mb/s (USB 2.0) Full is 12 Mb/s (USB 1.1) Low is 1.5 Mb/s (USB 1.0) New Super Speed, 5Gb/s!! (USB 3.0) High speed starts as full, then handshakes and transitions High and low speeds interpret zeros and ones inverted 26
Coding NRZI Non-Return to Zero Inverted Transition if sending 0, none if sending 1 Bit stuffing Since a string of 1s causes no transitions, synchronization may be lost A zero is stuffed in after six consecutive ones Sync field Each packet starts with a sync 8 bits: 00000001 27
Packets Won t go into details 28
Summary Many types of I/O memory-mapped is most common different devices given different address ranges many different device protocols PS/2: keyboard, mice RS-232: serial ports USB: most common today also Firewire, Thunderbolt, ethernet also monitors, displays we did VGA (other higher resolutions also possible) DVI is most common today 29
