Solving PWM Trip Occurrence with CLB Constraint
Normal PWM
50%
50%
CMPSS_TRIPL
Req. PWM
50%
TRIP occurs
TRIP for period
--------------------
Resume PWM
50%
50%
50%
CMPA
TBPRD
Scenario:
Proposed Solution using CLB
Constraint: Having a 50% Duty cycle at all times even if trip occurs
S0
S1
S2
S3
S0: Keep original PWM signals
S1: Keep original PWM signals
S2: Set outputs to certain
state
S3: Keep outputs to certain
state
CMPSS trip
Occurs
On falling edge of
PWM signal
If trip occurs again
during period and CTR
has not reached
period
TBCTR == Period
and no trip
TBCTR ==
Period
Normal PWM
50%
50%
CMPSS_TRIPL
Req. PWM
50%
TRIP occurs
TRIP for period
--------------------
Resume PWM
50%
50%
50%
CMPA
TBPRD
Theoretical solution scenario 1:
S0
S1
S2
S0
Normal PWM
50%
50%
CMPSS_TRIPL
Req. PWM
50%
TRIP occurs
TRIP for period
--------------------
Set outputs PWM
50%
50%
CMPA
TBPRD
Theoretical solution scenario 2:
S0
S1
S
2
S2
S3
Resume PWM
S0
In a scenario where PWM tripping occurs, a proposed solution utilizing CLB constraints ensures a consistent 50% duty cycle even during trips. The theoretical solutions provide detailed sequences for maintaining PWM signals and outputs, effectively managing trip occurrences. Explore theoretical scenarios with CLB constraints for handling PWM trip interruptions seamlessly.
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Presentation Transcript
Scenario: TBPRD CMPA 50% 50% 50% Normal PWM TRIP occurs CMPSS_TRIPL Resume PWM TRIP for period -------------------- Req. PWM 50% 50% 50%
Proposed Solution using CLB Constraint: Having a 50% Duty cycle at all times even if trip occurs S0: Keep original PWM signals S1: Keep original PWM signals S2: Set outputs to certain state S3: Keep outputs to certain state S0 CMPSS trip Occurs TBCTR == Period and no trip S3 S1 TBCTR == Period On falling edge of PWM signal If trip occurs again during period and CTR has not reached period S2
Theoretical solution scenario 1: TBPRD CMPA S0 50% 50% 50% Normal PWM TRIP occurs S0 CMPSS_TRIPL S1 Resume PWM TRIP for period -------------------- Req. PWM 50% 50% 50% S2
Theoretical solution scenario 2: TBPRD CMPA S0 50% 50% 50% Normal PWM S0 TRIP occurs CMPSS_TRIPL S1 Set outputs PWM Resume PWM TRIP for period -------------------- S2 Req. PWM 50% 50% S 2 S3
