SLAC CRYO: Waveform Digitizer/Serializer for Cryogenic TPC Experiments

SLAC is developing the CRYO ASIC, a high-performance waveform digitizer and serializer optimized for cryogenic operation in experiments like DUNE. The CRYO ASIC offers advanced features such as single-chip integration, programmability, on-chip regulation, and design for reliability. Operating in a 130nm CMOS process, it boasts impressive specifications including high input capacitance, anti-alias filters, multiple gains, and a wide temperature range. The architecture includes elaborate digital and analog sections for efficient data processing and transmission.

• SLAC
• CRYO ASIC
• Waveform Digitizer
• Cryogenic TPC
• DUNE Experiment

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1. CRYO CRYO: : a Waveform Digitizer/Serializer for Cryogenic TPC Experiments TID AIR Integrated Circuits Department* *dragone@slac.stanford.edu SLAC TID-AIR Technology and Innovation Directorate Advanced Instrumentation for Research Division

2. Outline Introduction Specifications Cryo Architecture Simulation Results Progress Status Conclusions 2

3. Introduction SLAC is designing a waveform digitizing ASIC (named CRYO ) for cryogenic operation optimized for the charge readout of DUNE experiment Key features of Cryo: - Implements analog and digital functionalities in a single ASIC (SoC approach) - Minimum I/O pins - Highly programmable to change functionalities and operation points across temperature - On chip regulation (single external supply) - Design for reliability and testability (critical sections can be reconfigured to be tested independently and bypassed if needed) ASIC design is implemented in 130nm CMOS technology - Technology characterized at SLAC 3

4. Specifications 130 nm CMOS process ~ 220pF Input capacitance Bessel 5th Order (P.T. 0.6us, 1.2us, 2.4us, 3.6us) Anti-Alias filter 6X, 3X, 1.5X, 1X (50fC, 100fC, 200fC, 300fC) Multiple gains (max signal) ALARA (~500e- @ 0.5X, 1.2us) Noise 12bit Dynamic Range 2MSPS Sampling Freq. 87 K (-186 C) Temperature 4

5. CRYO Architecture VSEXT_25 VGEXT_25 Digital Domain (Isolated) X8 (Bank) Digital MUX Serializer 12b/14b Encoder Out0 LVDS Transmitter 896Mbps SubBank FE LDO2_Bk0 BE LDO3_Bk0 FE LDO0_Bk0 FE LDO1_Bk0 Receiver BE LDO4_LVDS X8 (Bank) Digital MUX Serializer 12b/14b Encoder Out1 LVDS Transmitter 896Mbps SACI x4 PLL (LVDS) CLK BE LDO3_Bk1 FE LDO0_Bk1 FE LDO2_Bk1 FE LDO1_Bk1 CU LDO5_Ctrl Control Unit Global Control Register 5

6. CRYO Architecture VSEXT_25 VGEXT_25 Digital Domain (Isolated) X8 (Bank) ANALOG Digital MUX Serializer 12b/14b Encoder Out0 LVDS Transmitter 64 channels are divided in two sections (Banks) 896Mbps SubBank BE LDO3_Bk0 Each Bank contains 32-channels FE LDO2_Bk0 FE LDO0_Bk0 FE LDO1_Bk0 Receiver BE LDO4_LVDS X8 (Bank) Charge sensitive amplifier, Bessel Filter, and S/H implement the channel Digital MUX Serializer 12b/14b Encoder Out1 LVDS Transmitter 4-to-1 multiplexing of channels into a single ADC 896Mbps SACI x4 PLL (LVDS) CLK BE LDO3_Bk1 On-chip distributed supply regulation (LDOs) FE LDO0_Bk1 FE LDO2_Bk1 FE LDO1_Bk1 CU LDO5_Ctrl Control Unit Global Control Register 6

7. CRYO Architecture VSEXT_25 VGEXT_25 Digital Domain (Isolated) X8 (Bank) DIGITAL Digital MUX Serializer 12b/14b Encoder 12b/14b data encoding Out0 LVDS Transmitter 896Mbps Serialization and LVDS data transmission at 896Mbps SubBank FE LDO2_Bk0 BE LDO3_Bk0 FE LDO0_Bk0 FE LDO1_Bk0 Receiver Dedicated control unit (SACI) to control BE LDO4_LVDS X8 (Bank) functions of analog and digital blocks Digital MUX Serializer 12b/14b Encoder Digital activity is isolated in Deep N-Well (DNW) Out1 LVDS Transmitter 896Mbps SACI x4 PLL (LVDS) CLK FE LDO0_Bk1 Wen-Kuan Yeh et al. Solid State Devices and Materials Tokyo, 2003, pp. 408-409 BE LDO3_Bk1 FE LDO2_Bk1 FE LDO1_Bk1 CU LDO5_Ctrl Control Unit Global Control Register 7

8. CRYO Architecture Main Analog Blocks SAR ADC Analog Front-End (FE) Channel Rf CTRL <0:11> (x3) VINP Cf C4 C11 C10 C5 C0 CD 32Cu 16Cu Cu 16Cu Cu Cu N*Rf CA = 32/31Cu Qin DAC P-CH N*Qin VREFP DATA <0:11> EOC CLK SAR Logic VCM VREFN DAC N-CH Vcm-Based CA = 32/31Cu CDET IDET C4 C11 C10 C5 C0 CD N*Cf 32Cu 16Cu Cu 16Cu Cu Cu Bessel Zero Pole VINN CTRL <0:11> (x3) [G. De Geronimo, IEEE TNS2000] [Y. Zhu et. al. , JSSC2010] Key Features Preamplifier with pole-zero cancellation Highly programmable Effective linear charge amplification (N) 5th - Order Bessel filter - Avoids aliasing - Optimize SNR - Flat group delay (low distortion) - Short impulse response with no ripples - Programmable peaking time Key features Fully differential configuration Split cap DAC based on VCM switching Eliminates the MSB capacitor x2 area improvement wrt conv. split config. x2 DNL improvement wrt conv. split config. Reduction of switching energy by ~80% Cu = 62fF MIM cap (meets noise and linearity) Offset Calibration 8

9. CRYO Architecture Main Analog Blocks Low Drop Out Voltage Linear Regular (LDOs) Key features LDO1 Low noise amplifier to drive Analog Front-End LDO2 Low power amplifier to drive Digital Back-End Current drive capability: 70 mA and 140 mA load Stable at no current load External output capacitor (IPDIA Si Cap of 4.7 uF) Programmable output voltage: - 2V for Analog - 1V for Digital LDO1 Low noise amplifier LDO2 Low power amplifier Simulation results of LDO1 at 87K (-186 C) Worst case across corners Vn Vn PM (deg) Adc (dB) PSRR @ DC Worst PSRR @ >100 MHz Parameter @1 KHz @100 KHz 2.7 nV/ (Hz) 0.9 nV/ (Hz) >90 46 51 dB 9.5 dB IL=0 ( IQ~7mA ) 2.7 nV/ (Hz) 1.3 nV/ (Hz) >90 40 41 dB 2.9 dB IL=40 mA ( IQ~7mA) 9

10. Simulated Channel Response Bessel Case: gain 3X, Qin = 100fC Programmable Peaking Time (1%-100%) 0.6us, 1.2us, 2.4us, 3.6us Vo [V] Time [sec] The bandwidths at these peaking times are equivalent to the bandwidths of a SGCP with peaking times (1%-100%) 0.5us, 1us, 2us, 3us 10

11. Simulated Channel Response Bessel Programmable Gain (6X, 3X, 1.5X, 1X) Qin = 50fC, 100fC, 200fC and 300fC Vo [V] Time [sec] Case: peaking time = 1.2us 11

12. Simulated Channel Response Total ENC [e-] Input Transistor ENC [e-] Case: gain 3x, peaking time = 1.2us 12

13. Simulated Channel Response Case: gain 3X 13

14. Top Level Simulations Entire Backend Test Bench Functional simulation of two Banks 64 Channels x16 ADCs Test Bench includes: LDOs (top and bottom) x2 Banks (Bk0 and Bk1) Each bank contains: x16 SAHs, x8 Analog MUXs, x8 ADCs, x4 Amplifier Buffers, Logic x2 digital readout circuit (digital mux, encoder, serializer) PLL, Duty-Cycle adjustment and clock distribution x1 LVDS Rx (PLL clk input) and x2 LVDs Tx (outputs of the chip) FE is bypassed Sinewave test signal (Fin =~248KHz, Ampl = 1.54Vpp) is applied at the input of all S/Hs (x64) Temperature: 87K (-186C) Synopsys CustomSim simulator - Level 3 14

15. Top Level Simulations Entire Backend 15

16. Top Level Simulations Entire Backend External Caps + Wire bonding LDOs DigRO Top Bank Out_Data LVDS PLL, Dcycle, Clk Bottom Bank Out_Data LVDS LDOs External Caps + Wire bonding 16

17. Top Level Simulations Entire Backend ADC Signals x16 ADCs are running but only the 12-bit output of x6 ADCs are quantized using ideal DACs PLL Signal ADC Clk Signal Top Bank ADC outputs (Quantized Version) Bottom Bank ADC outputs (Quantized Version) Top Bank Output Bitstream (LVDS Tx) Bottom Bank Output Bitstream (LVDS Tx) 17

18. Top Level Simulations Entire Backend SPICE-on-Top Verification Flow Using Verilog/VHDL SPICE Top Bank Output Bitstream (LVDS Tx) Bottom Bank Output Bitstream (LVDS Tx) VHDL Digital flow (Deserialization/Decoding) is applied to the data bitstream of the two LVDS Tx outputs The post-processed data is compared with analog waveforms of the TB 18

19. Top Level Simulations Entire Backend Comparison Results - VHDL vs SPICE SubBank0 Top Bank Digital Flow with HDL LVDS Tx Output 8 SubBanks 32 Channels Spice Simulation ADC Outputs of Top Bank SubBank3 SubBank7 SubBank15 Bottom Bank Digital Flow with HDL LVDS Tx Output 8 SubBanks 32 Channels Spice Simulation ADC Outputs of Bottom Bank SubBank12 SubBank8 19

20. Top Level Simulations Performance ADC Performance Simulation Test Bench includes: LDOs PLL and Digital RO LVDS of Bank 0 Bank 0 Two Sub-Banks (3 & 7) 8 Channels, 2 ADCs Biasing and Reference Voltages 0dB PSD 2 Channels Ampl = 0.77V (-0.3dBFS) Fin = 248.1k 1024 FFT Points TT case PSD [dB] CH12 CH28 Transient Simulation CustomSim - level 6 -120dB Freq [Hz] 0 1M CH12 11.53 bit CH28 11.56 bit CH13 11.46 bit CH29 11.43 bit CH14 11.45 bit CH30 11.49 bit CH15 11.61 bit CH31 11.60 bit SubBank 3 SubBank 7 20

21. Progress Status Completed All blocks laid out and verified Placement of blocks completed Core interconnection completed In progress Interconnections to periphery blocks and pad ring Full chip simulation (with front-end) To be done (about 4 weeks) Power distribution net Filling Full chip verification Goal is to use the end of June fabrication run 21

22. ASIC characterization collaboration Established collaboration: SLAC, University of Pennsylvania, University of Hawaii, UC Davis plus BNL (under discussion) Weekly meeting to discuss testing plans Baseline is to reuse SLAC cryogenic setup Cold test board designed Initial DAQ board reuses SLAC ePix DAQ SAMTEC cable characterization - Model extracted both at SAMTEC and at SLAC and used in ASIC simulation Studies of packaging solutions minimizing mechanical stress in progress Studies interconnections and required feature for a CRYO compatible WIB in progress 22

23. Conclusions Full-chip simulations in progress - showing correct behavior with parasitics embedded in critical blocks - Key performance metrics met in simulation Layout well underway - Core section completed - Entire placement completed - Remaining tasks: Interconnections to periphery Power distribution / filling Full chip Verification Fabrication and testing still on track for the November test - Delays occurred due to Complexity Limited funding Limited manpower (lost one designer 2 position open in case someone is interested) - New target fabrication run is end of June - Testing plan defined (SLAC, U. Penn, U. Hawaii, UC Davis, BNL) 23