Overview of SpaceWire RMAP IP Core and Applications

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SpaceWire RMAP
IP Core
 
Steve Parkes, Chris McClements, Martin Dunstan
 
Space Technology Centre, University of Dundee
Wahida Gasti
 
ESTEC
 
1
 
Contents
 
UoD / STAR-Dundee IP Cores
RMAP Overview
RMAP IP Core Context
Architecture
Testing
Performance
Current and Future Work
 
2
 
UoD / STAR-Dundee IP Cores
 
SpaceWire CODEC (ESA-b)
Widely used by European Space Industry
Used in four Atmel ASICs
AT7910E, AT7911E, AT7912E, AT7913E
Used in many FPGA designs
SpaceWire Router
Highly flexible
Highly capable
Used in AT7910E SpW-10X Router ASIC
JAXA-MMO SpW-RMAP Codec
Low speed operation SpaceWire CODEC
RMAP Target
Specialised IP cores
Used in STAR-Dundee products
 
3
 
RMAP Overview
 
Remote Memory Access Protocol
Provide a means of
Writing to
Reading from
Registers or memory on a SpaceWire node
Over a SpaceWire network
Registers are considered to be memory mapped
Simple and effective
Flexible
Encompassing diverse applications
Being used on Bepi Colombo, MMS, ExoMars, ...
ECSS standard
Issued standard expected early 2009
 
4
Context - RMAP Initiator
5
Initiator
User
Logic
Initiator
RMAP
Interface
SpW
Interface
Context - RMAP Target
6
Target
Memory
Target
RMAP
Interface
SpW
Interface
Context - RMAP Initiator Reply
7
Initiator
User
Logic
Initiator
RMAP
Interface
SpW
Interface
Context
8
SpaceWire Network
RMAP Write Command
9
Target Logical Addr
Protocol Identifier
Instruction
Key
Initiator Logical Addr
Header CRC
EOP
RMAP Write Reply
10
Initiator Logical Addr
Protocol Identifier
Instruction
Status
Target Logical Addr
EOP
11
SpaceWire
Interface
RMAP
Handler
DMA
Controller
User Memory/
RegisterBus
SpaceWire
Network
Target Architecture
12
U
s
e
r
I
n
t
e
r
f
a
c
e
S
p
a
c
e
W
i
r
e
Initiator Architecture
13
S
p
a
c
e
W
i
r
e
RMAP
Master
Controller
U
s
e
r
I
n
t
e
r
f
a
c
e
 
Configurable IP Core
 
Highly configurable RMAP IP Core
E.g.
Data bus width
Endian-ness
Bit Swapping
Verify buffer size
DMA burst size
DMA watchdog
Loop back enable
Initiator/Target
RMAP send reply on EEP
...
 
 
 
14
 
Testing
 
RMAP Target
Extensive test bench
Full code coverage
All error conditions exercised
Implemented in Xilinx FPGA
Implemented in Actel AX1000
 
15
Xilinx Test Board
16
FPGA
Daughterboard
SpW
Breakout
Connectors
Actel AX1000 Test Board
17
Actel
AX1000
LVDS
Xilinx
FPGA
 
Performance RMAP Target
 
Xilinx Spartan-3 FPGA
200 Mbits/s transmit and receive
RMAP core handles data at these speeds
 
Actel AX1000 FPGA
Initial implementation
100 Mbits/s transmit
150 Mbits/s receive
 
18
 
Footprint
 
Initial results:
 
Xilinx Virtex IV (4VFX20)
889 CLBs (10.4%) RMAP core only
1168 CLBs (13.7%) RMAP + SpW
 
Actel AX1000
2025 modules (17%) RMAP core only
4551 modules (26%) RMAP + SpW
 
19
 
Current and Future Work
 
Currently working on initiator design
Once complete will optimise Actel FPGA
performance
Two alpha customers running tests on RMAP
IP core
 
20
 
Availability
 
Available from ESA for use on ESA projects
only
Available from STAR-Dundee for all other
projects
 
21
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This content provides an overview of the SpaceWire RMAP IP Core developed by Steve Parkes, Chris McClements, and Martin Dunstan from the Space Technology Centre at the University of Dundee, along with Wahida Gasti from ESTEC. It discusses the architecture, testing, performance, and current/future work related to this core. Additionally, it highlights the usage of the UoD/STAR-Dundee IP Cores, particularly the SpaceWire CODEC widely used in the European space industry. The content also delves into the RMAP protocol, its features, applications, and usage in various space missions. Images are included to illustrate the concepts discussed.

  • SpaceWire
  • RMAP
  • IP Core
  • Space Technology
  • European Space Industry

Uploaded on May 14, 2024 | 5 Views


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  1. SpaceWire RMAP IP Core Steve Parkes, Chris McClements, Martin Dunstan Space Technology Centre, University of Dundee Wahida Gasti ESTEC 1

  2. Contents UoD / STAR-Dundee IP Cores RMAP Overview RMAP IP Core Context Architecture Testing Performance Current and Future Work 2

  3. UoD / STAR-Dundee IP Cores SpaceWire CODEC (ESA-b) Widely used by European Space Industry Used in four Atmel ASICs AT7910E, AT7911E, AT7912E, AT7913E Used in many FPGA designs SpaceWire Router Highly flexible Highly capable Used in AT7910E SpW-10X Router ASIC JAXA-MMO SpW-RMAP Codec Low speed operation SpaceWire CODEC RMAP Target Specialised IP cores Used in STAR-Dundee products 3

  4. RMAP Overview Remote Memory Access Protocol Provide a means of Writing to Reading from Registers or memory on a SpaceWire node Over a SpaceWire network Registers are considered to be memory mapped Simple and effective Flexible Encompassing diverse applications Being used on Bepi Colombo, MMS, ExoMars, ... ECSS standard Issued standard expected early 2009 4

  5. Context - RMAP Initiator SpaceWire Packet Containing RMAP Command Request to Send RMAP Command RMAP Command Initiator User Logic Initiator RMAP Interface SpW Interface 5

  6. Context - RMAP Target SpaceWire Packet Containing RMAP Command Write/Read /RMW Operation RMAP Command Target RMAP Interface SpW Interface Target Memory SpaceWire Packet Containing RMAP Reply Any Data Read RMAP Reply 6

  7. Context - RMAP Initiator Reply Initiator User Logic Initiator RMAP Interface SpW Interface SpaceWire Packet Containing RMAP Reply Status, Error Code, Or Data RMAP Reply 7

  8. Context INITIATOR ONLY NODE SpW I/F INITIATOR/TARGET NODE INI User SpaceWire Network User INI TARGET ONLY NODE SpW I/F SpW I/F TGT Mem Mem TGT TARGET ONLY NODE SpW I/F TGT Mem 8

  9. RMAP Write Command First byte transmitted Target SpW Address .... Target SpW Address Target Logical Addr Reply Address Reply Address Protocol Identifier Reply Address Reply Address Instruction Reply Address Reply Address Key Reply Address Reply Address Reply Address Reply Address Reply Address Reply Address Initiator Logical Addr Transaction ID (MS) Transaction ID (LS) Extended Address Address (MS) Address Data Length (MS) Data Length Data Data Data ... Data Data CRC Address (LS) Header CRC Data Data Address Data Length (LS) Data ... EOP Last byte transmitted 9

  10. RMAP Write Reply First byte transmitted Reply SpW Address .... Reply SpW Address Initiator Logical Addr Protocol Identifier Instruction Status Target Logical Addr Transaction ID (MS) Transaction ID (LS) Header CRC Last byte transmitted EOP 10

  11. SpaceWire Network SpaceWire Interface RMAP Handler DMA Controller User Memory/ RegisterBus SpaceWire RMAP Command RMAP Header Check Header Address Data length RMAP Data Authorisation Request Authorisation Grant Check Data Start Bus Request Bus Grant Start Ack Address Data Data Data Data Relinquish Bus Done RMAP Reply Indicate SpaceWire RMAP Reply 11

  12. Target Architecture User Interface RMAP Initiator Handler Initiator DMA Cntrl SpaceWire Protocol De-Mux SpW Packet Loop- Back Target DMA Cntrl RMAP Target Handler SpW I/F Protocol Mux Time- Code Handler 12

  13. Initiator Architecture User Interface SpaceWire Time-Code Handler Non RMAP SpaceWire Interface Protocol De-Mux SpW Packet Loop- Back RMAP RMAP Master Controller Non RMAP DMA Controller Protocol Mux RMAP 13

  14. Configurable IP Core Highly configurable RMAP IP Core E.g. Data bus width Endian-ness Bit Swapping Verify buffer size DMA burst size DMA watchdog Loop back enable Initiator/Target RMAP send reply on EEP ... 14

  15. Testing RMAP Target Extensive test bench Full code coverage All error conditions exercised Implemented in Xilinx FPGA Implemented in Actel AX1000 15

  16. Xilinx Test Board Breakout Connectors FPGA SpW Daughterboard 16

  17. Actel AX1000 Test Board Actel AX1000 Xilinx FPGA LVDS 17

  18. Performance RMAP Target Xilinx Spartan-3 FPGA 200 Mbits/s transmit and receive RMAP core handles data at these speeds Actel AX1000 FPGA Initial implementation 100 Mbits/s transmit 150 Mbits/s receive 18

  19. Footprint Initial results: Xilinx Virtex IV (4VFX20) 889 CLBs (10.4%) RMAP core only 1168 CLBs (13.7%) RMAP + SpW Actel AX1000 2025 modules (17%) RMAP core only 4551 modules (26%) RMAP + SpW 19

  20. Current and Future Work Currently working on initiator design Once complete will optimise Actel FPGA performance Two alpha customers running tests on RMAP IP core 20

  21. Availability Available from ESA for use on ESA projects only Available from STAR-Dundee for all other projects 21

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