Overview of CMOS Process in Microelectronic Design
The CMOS Process
P. Bruschi – Microelectronic System Design
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Classification of planar CMOS processes: example
CMOS n-well 0.18
m 1P6M
Minimum channel length
Type of Well (n-well, p-well, triple-well)
Number of poly layers
Number of metal layers
Simplified designer's view of a CMOS Process
P. Bruschi – Microelectronic System Design
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We are considering a simple n-well (twin-Tub) 1P2M process
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N-wells are insulated from the substrate if the latter is biased at the
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A very lightly doped epitaxial layer is often present on top of a strongly
doped wafer. P-wells are necessary to obtain the optimal doping for n-
MOSFETS.
The active areas
P. Bruschi – Microelectronic System Design
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Top view
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Polysilicon and gate oxide
P. Bruschi – Microelectronic System Design
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After that, it is covered by the polysilicon layer
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When the poly is patterned, the gate oxide remains only where
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Only one layer (poly) is required to control the final result of this step.
poly over active area
MOSFET gate
poly out of active area
inteconnection
FEOL (Front-End Of the Line)
P. Bruschi – Microelectronic System Design
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BEOL (Back End Of the Line) - Contacts
P. Bruschi – Microelectronic System Design
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Contacts can reach active areas (p+ or n+ doped portions of the
substrate) or polysilicon (over the FOX).
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Direct contact of polysilicon over the gates is not allowed
Insulating
Layer
Contacts
Thungsten
Plugs
BEOL: The interconnections
P. Bruschi – Microelectronic System Design
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Bonding Pads
P. Bruschi – Microelectronic System Design
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Layer: Passivation Opening
The Triple Well
P. Bruschi – Microelectronic System Design
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n-well
n-well
n-well twin tub
buried well o buried layer
Triple Well: Multiple PWells and NWells at independent voltages
P. Bruschi – Microelectronic System Design
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Bipolar processes
P. Bruschi – Microelectronic System Design
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BiCMOS, BCD, SOI
P. Bruschi – Microelectronic System Design
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Resistances in planar ICs
P. Bruschi – Microelectronic System Design
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Direction of the current
/ square
Number of
squares
W
Vertical and lateral capacitances
P. Bruschi – Microelectronic System Design
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Capacitance per unit area
Capacitance per unit perimeter
(Fringe capacitance)
Area
Perimeter
Lateral and Junction Capacitances
P. Bruschi – Microelectronic System Design
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Lateral
Junction
p (or n)
n (or p)
The CMOS process involves both planar and 3D CMOS technologies for different technology nodes. Planar CMOS processes, like CMOS n-well 0.18μm 1P6M, are still widely used for analog and mixed-signal ICs. This process includes steps like creating active areas, depositing polysilicon and gate oxide for MOSFETs, Front-End-Of-the-Line (FEOL) processes, Back-End-Of-the-Line (BEOL) with contacts and interconnections. Images illustrate the key stages of the CMOS process in microelectronic system design.
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Presentation Transcript
The CMOS Process Planar CMOS process is used up to the 28 nm technology node. For later technology nodes, 3D CMOS MOSFETs (FinFETs) are used. Planar CMOS processes are still extensively used for analog and mixed-signal ICs. Classification of planar CMOS processes: example CMOS n-well 0.18 m 1P6M Number of metal layers Minimum channel length Number of poly layers Type of Well (n-well, p-well, triple-well) P. Bruschi Microelectronic System Design 1
Simplified designer's view of a CMOS Process We are considering a simple n-well (twin-Tub) 1P2M process The starting substrate is p-type: all p-wells are shorted together since there are no insulation junctions with the substrate. N-wells are insulated from the substrate if the latter is biased at the lowest voltage in the circuit. A very lightly doped epitaxial layer is often present on top of a strongly doped wafer. P-wells are necessary to obtain the optimal doping for n- MOSFETS. P. Bruschi Microelectronic System Design 2
The active areas Active areas are all of the same type. They are specialized by other layers (e.g. n-well). p-wells are often drawn automatically as not(n-well) n-well Top view P. Bruschi Microelectronic System Design 3
Polysilicon and gate oxide poly over active area MOSFET gate poly out of active area inteconnection The gate (thin) oxide is grown on all active areas. After that, it is covered by the polysilicon layer When the poly is patterned, the gate oxide remains only where polysilicon remains, forming the gate. Only one layer (poly) is required to control the final result of this step. P. Bruschi Microelectronic System Design 4
FEOL (Front-End Of the Line) P. Bruschi Microelectronic System Design 5
BEOL (Back End Of the Line) - Contacts All devices created in the FEOL are covered by an insulating layer and holes are opened only where we want to contact them. These opening are the CONTACTS Contacts can reach active areas (p+ or n+ doped portions of the substrate) or polysilicon (over the FOX). Direct contact of polysilicon over the gates is not allowed Contacts Insulating Layer Thungsten Plugs P. Bruschi Microelectronic System Design 6
BEOL: The interconnections P. Bruschi Microelectronic System Design 7
Bonding Pads Layer: Passivation Opening P. Bruschi Microelectronic System Design 8
The Triple Well n-well twin tub n-well n-well buried well o buried layer P. Bruschi Microelectronic System Design 9
Triple Well: Multiple PWells and NWells at independent voltages P. Bruschi Microelectronic System Design 10
Bipolar processes Technology Available Devices Notes Bipolar Vertical NPN, Lateral PNP Used for precision and/or fast amplifier. Si-Ge versions for RF applications Complementary Bipolar Vertical NPN, Vertical PNP BiFet BJTs and JFETs Used for precision / low bias current amplifiers P. Bruschi Microelectronic System Design 11
BiCMOS, BCD, SOI Technology Available Devices Notes BiCMOS CMOS + BJTs Mixed Signal ICs High speed digital line drivers Smart Power BCD Bipolar, CMOS, DMOS SOI Insulator. Silicon on As CMOS, BiCMOS or BCD High Voltage and Rad Hard (e.g. space applications) P. Bruschi Microelectronic System Design 12
Resistances in planar ICs / square Number of squares Direction of the current W L = R R S W P. Bruschi Microelectronic System Design 13
Vertical and lateral capacitances = = Area A P W W W A B + 2 2 W Perimeter A B = k A k P + C V A P Capacitance per unit area Capacitance per unit perimeter (Fringe capacitance) P. Bruschi Microelectronic System Design 14
Lateral and Junction Capacitances n (or p) p (or n) L t Junction = Lateral m C L d d = + C C A C P n p J JSW P. Bruschi Microelectronic System Design 15
