Mapping Schemes Presentation for DSN Group Meeting
This presentation outlines various mapping schemes discussed during a DSN group meeting at Sharif University of Technology. The schemes include page-level mapping, demand-based flash translation layer, block-level mapping, hybrid-level mapping, and more. Each scheme is detailed with advantages, disadvantages, and key features. The presentation provides insights into managing NAND flash memory efficiently and optimizing read/write performance.
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Presentation Transcript
Different Mapping Schemes Presentation for DSN Group Meeting By: Reza Faridmoayer Supervisor: Dr. Asadi Sharif University of Technology, Department of Computer Engineering May 31, 2011
Outline Page-Level Mapping Scheme Demand-based Flash Translation Layer (DFTL) Convertible Flash Translation Layer (CFTL) Block-Level Mapping Scheme Hybrid-Level Mapping Scheme (next presentation) Fully Associative Sector Translation (FAST) Flexible management Flexible group-mapping 3/2/2025 2 Sharif University of Technology, Department of Computer Engineering
Outline(cont.) Hybrid-Level Mapping Scheme (Cont.) Locality Aware Sector Translation (LAST) Log-based Flash Translation Layer (LogFTL) Switchable Address Translation (SAT) Filtering Flash Translation Layer (FFTL) 3/2/2025 3 Sharif University of Technology, Department of Computer Engineering
Page-Level Mapping Scheme Managing the NAND flash memory on page basis A page mapping table: Logical Page Numbers (LPNs) Physical Page Numbers (PPNs) Maintaining page mapping table in both RAM and NAND flash memory Advantage o Good read/write performance because of its high block utilization 3/2/2025 4 Sharif University of Technology, Department of Computer Engineering
Page-Level Mapping Scheme (cont.) Disadvantages o Increasing the number of invalid pages dramatically reducing the performance o A very large space in both RAM & NAND flash memory to store the original page table The example of page-level mapping 3/2/2025 5 Sharif University of Technology, Department of Computer Engineering
Demand-based Flash Translation Layer (DFTL) A new mapping scheme Storing the entire mapping table on flash memory instead of SRAM Cache the most recently used mappings information DFTL Architecture o Cached Mapping Table (CMT) o Global Translation Directory (GTD) 3/2/2025 7 Sharif University of Technology, Department of Computer Engineering
DFTL Architecture Tracks translation pages on flash Stores active address mapping Global Translation Directory MvPN Cached Mapping Table Consult location of translation Consult location of translation pages on flash pages on flash MPPN DLPN DPPN Directory Entries Mapping Entries Store real data from I/O requests Fetch mapping entry SRAM Evict mapping entry for Evict mapping entry for synchronization synchronization Fetch mapping Fetch mapping entry entry FLASH Data blocks Translation blocks 3/2/2025 Sharif University of Technology, Department of Computer Engineering 8
Demand-based Flash Translation Layer (DFTL) (Cont.) Advantages o The high utilization of the blocks space o Better write performance than hybrid-level mapping scheme under write dominant workloads o Removes the full merge operations Disadvantages o Consideration temporal locality for data access o Suffering from the frequent updates of translation pages for write-intensive workloads 3/2/2025 9 Sharif University of Technology, Department of Computer Engineering
Demand-based Flash Translation Layer (DFTL)(Cont.) The example of DFTL DLPN=1280 Cached Mapping Table Global Translation Directory (1) (7) DLPN DPPN 3 10 170 MVPN MPPN (2) (6) 150 0 21 17 23 1 Data Page 11 220 1 2 15 22 260 3 (3) (8) (5) (10) SRAM 1280 660 (11) (9) MPPN=15 MPPN=21 DPPN=660 DPPN=661 MPPN=23 DLPN 0 1 2 - DPPN 110 130 440 - DLPN 0 1 2 - DPPN 110 130 440 DLPN 1024 570 - 1280 660 DPPN - 260 ... ... Data - - - 511 560 560 511 1535 420 OBB MVPN=0 DLPN=1280 MVPN=2 MVPN=0 (4) Data Block Translation Block 3/2/2025 10 Sharif University of Technology, Department of Computer Engineering
Convertible Flash Translation Layer (CFTL) A workload behavior FTL scheme Takes advantage of page-level and block-level mapping scheme Page-level and block-level mapping schemes to manage write- intensive workloads and read-intensive workloads CFTL Architecture o Cached Block Mapping Table (CBMT) o Cached Page Mapping Table (CPMT) o Tier-1 Page Mapping Table 3/2/2025 11 Sharif University of Technology, Department of Computer Engineering
Convertible Flash Translation Layer (CFTL) (Cont.) DFTL and CFTL comparison DFTL CFTL Mapping Table Stored in Flash Flash Write Intensive Workload Performance Good Good Read Intensive Workload Performance Not Good Good Exploits Temporal Locality Yes Yes Exploits Spatial Locality No Yes Adaptiveness No Yes 3/2/2025 Sharif University of Technology, Department of Computer Engineering 13
Convertible Flash Translation Layer (CFTL) (Cont.) The example of CFTL 3/2/2025 Sharif University of Technology, Department of Computer Engineering 14
Block-level Mapping Scheme Managing the NAND flash memory on block basis A block mapping table: Logical Block Numbers (LBNs) Physical Block Numbers (PBNs) Maintaining block mapping table in both RAM and NAND flash memory Advantage o Smaller space of RAM and NAND flash 3/2/2025 Sharif University of Technology, Department of Computer Engineering 15
Block-level Mapping Scheme (Cont.) Disadvantage o The block copy overhead The example of block-level mapping scheme 3/2/2025 Sharif University of Technology, Department of Computer Engineering 16
THANK YOU FOR YOUR ATTENTION 3/2/2025 Sharif University of Technology, Department of Computer Engineering 18
