Integrated Circuits and Logic Circuits
EECS 370 Discussion
1
xkcd.com
EECS 370 Discussion
Topics Today:
–
Floating Point
–
Finite State Machines
–
Combinational Logic
–
Sequential Logic
2
EECS 370 Discussion
Floating Point
Exponent
Biased by 127
Significand
Additional 1 before the decimal sign
3
EECS 370 Discussion
Floating Point
Don’t forget about zero!
4
EECS 370 Discussion
Floating Point
Addition
-1.1011*(2
2
) + 1.01*(2
0
)
5
EECS 370 Discussion
Floating Point
Addition
-1.1011*(2
2
) + 1.01*(2
0
)
= -1.0110*(2
2
)
6
EECS 370 Discussion
Floating Point
Addition
-1.1011*(2
2
) + 1.01*(2
0
)
[-6.75] [1.25]
= -1.0110*(2
2
)
[-5.5]
7
EECS 370 Discussion
Floating Point
Multiplication
-1.1011*(2
2
) * 1.01*(2
0
)
[-6.75] [1.25]
8
EECS 370 Discussion
Floating Point
Multiplication
-1.1011*(2
2
) * 1.01*(2
0
)
[-6.75] [1.25]
= -1.0000111*(2
3
)
9
EECS 370 Discussion
Floating Point
Multiplication
-1.1011*(2
2
) * 1.01*(2
0
)
[-6.75] [1.25]
= -1.0000111*(2
3
)
[-8.4375]
10
EECS 370 Discussion
Finite State Machines
Diagram of State, Conditions to change state, and Outputs
Conditions to change are based on inputs
11
EECS 370 Discussion
Finite State Machines
Example: Output a 1 on the pattern 001
States:
Pattern ‘1’
Pattern ‘0’
Pattern ‘00’
Pattern ‘001’ => Output = 1
12
EECS 370 Discussion
Combinational Logic
Digital circuit representing a Boolean equation
Truth tables!!
13
EECS 370 Discussion
Combinational Logic
More Complex Circuits:
Mux Decoder
14
EECS 370 Discussion
Combinational Logic
More Complex Circuits: Full Adder
Half Adder
15
EECS 370 Discussion
Combinational Logic
More Complex Circuits:
Ripple Carry Adder
16
EECS 370 Discussion
Combinational Logic
Propagation Delay
17
EECS 370 Discussion
Combinational Logic
Propagation Delay
Slows down the speed of your circuit!
18
EECS 370 Discussion
Combinational Logic
Most Complex Circuits:
Carry Look-ahead Adder
19
EECS 370 Discussion
Sequential Logic
Combinational Logic
Stateless
Output is direct function of current input
Sequential Logic
Stateful
Output is function of current input and past input
Clocked!
20
EECS 370 Discussion
Sequential Logic
Latches
SR Latch D Latch
21
EECS 370 Discussion
Sequential Logic
Flip Flops
Positive Edge Triggered
22
EECS 370 Discussion
Sequential Logic
Why do we want clocked logic?
Specifies a time by which all operations are “done”
Results before that time do not matter
23
Delays in combinational circuits are very real.
Here’s an example with a
ripple carry adder
.
AN EXAMPLE OF WHY THIS MATTERS
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The value of a goes from 7 to 1 here
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
There’s propagation delay before
the adder even starts to change
values.
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The value stabilizes
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The next clock edge comes along
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The latch opens up
(and shows new value)
The flip-flop grabs new value.
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
B changes now,
while the clock is still high.
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
Again, there’s propagation delay
before the adder starts to change.
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The value in the latch changes too!
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The next falling edge comes along
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The adder stabilizes.
Let’s zoom in on the interesting part.
AN EXAMPLE OF WHY THIS MATTERS
The latch locked with
the wrong value!
Integrated circuits (ICs) are made from silicon and contain gates to perform computations. These circuits can vary in complexity, from simple Boolean functions to complex CPUs. Learn about different types of IC packages and how multiplexers, decoders, comparators, and other circuits function in digital logic systems.
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Presentation Transcript
EECS 370 Discussion xkcd.com 1
EECS 370 Discussion Topics Today: Floating Point Finite State Machines Combinational Logic Sequential Logic 2
EECS 370 Discussion Floating Point Exponent Biased by 127 Significand Additional 1 before the decimal sign 3
EECS 370 Discussion Floating Point Don t forget about zero! 4
EECS 370 Discussion Floating Point Addition -1.1011*(22) + 1.01*(20) 5
EECS 370 Discussion Floating Point Addition -1.1011*(22) + 1.01*(20) = -1.0110*(22) 6
EECS 370 Discussion Floating Point Addition [-6.75] [1.25] -1.1011*(22) + 1.01*(20) = -1.0110*(22) [-5.5] 7
EECS 370 Discussion Floating Point Multiplication [-6.75] [1.25] -1.1011*(22) * 1.01*(20) 8
EECS 370 Discussion Floating Point Multiplication [-6.75] [1.25] -1.1011*(22) * 1.01*(20) = -1.0000111*(23) 9
EECS 370 Discussion Floating Point Multiplication [-6.75] [1.25] -1.1011*(22) * 1.01*(20) = -1.0000111*(23) [-8.4375] 10
EECS 370 Discussion Finite State Machines Diagram of State, Conditions to change state, and Outputs Conditions to change are based on inputs 11
EECS 370 Discussion Finite State Machines Example: Output a 1 on the pattern 001 States: Pattern 1 Pattern 0 Pattern 00 Pattern 001 => Output = 1 12
EECS 370 Discussion Combinational Logic Digital circuit representing a Boolean equation Truth tables!! 13
EECS 370 Discussion Combinational Logic More Complex Circuits: Mux Decoder A0 A1 A Out0 S C Out1 Out2 Out3 B 14
EECS 370 Discussion Combinational Logic More Complex Circuits: Full Adder Half Adder 15
EECS 370 Discussion Combinational Logic More Complex Circuits: Ripple Carry Adder 16
EECS 370 Discussion Combinational Logic Propagation Delay 17
EECS 370 Discussion Combinational Logic Propagation Delay Slows down the speed of your circuit! 18
EECS 370 Discussion Combinational Logic Most Complex Circuits: Carry Look-ahead Adder 19
EECS 370 Discussion Sequential Logic Combinational Logic Stateless Output is direct function of current input Sequential Logic Stateful Output is function of current input and past input Clocked! 20
EECS 370 Discussion Sequential Logic Latches SR Latch D Latch 21
EECS 370 Discussion Sequential Logic Flip Flops Positive Edge Triggered 22
EECS 370 Discussion Sequential Logic Why do we want clocked logic? Specifies a time by which all operations are done Results before that time do not matter 23
AN EXAMPLE OF WHY THIS MATTERS Delays in combinational circuits are very real. Here s an example with a ripple carry adder ripple carry adder.
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The value of a goes from 7 to 1 here
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. There s propagation delay before the adder even starts to change values.
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The value stabilizes
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The next clock edge comes along
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The latch opens up (and shows new value) The flip-flop grabs new value.
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. B changes now, while the clock is still high.
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. Again, there s propagation delay before the adder starts to change.
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The value in the latch changes too!
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The next falling edge comes along
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The adder stabilizes.
AN EXAMPLE OF WHY THIS MATTERS Let s zoom in on the interesting part. The latch locked with the wrong value!
