IBIS Interconnect: Models and Task Group Overview

The IBIS Interconnect draft explores models representing package and on-die interconnect, with separate or combined approaches for on-die, package, supply, and signal interconnect. The IBIS Interconnect Task Group, comprising major contributors such as Altera, Cadence Design Systems, Intel Corp, and others, meets weekly to advance interconnect modeling. The models support various languages and features like different interconnect combinations and end types. The document also touches on the similar approach for both IBIS and EBD interconnect models with details on terminals, pins, pads, buffers, and more.

• IBIS Interconnect
• Models
• Task Group
• Interconnect Language
• Signal Integrity

iannotti_j Follow

Uploaded on Sep 17, 2024 | 0 Views

Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

Presentation Transcript

1. IBIS Interconnect BIRD Draft 0 Walter Katz Signal Integrity Software, Inc. IBIS Summit, DesignCon January 27, 2015

2. Overview IBIS Interconnect Task Group Models Represent Package and On-Die Interconnect On Die, Package, Supply and Signal Interconnect can be Combines or Kept Separate Similar Approach for Both IBIS and EBD IBIS Interconnect Model Terminals Pre and Post Layout IBIS Files Corners [Interconnect Model Selector] [Interconnect Model] [Begin Model] Terminal Terminals Next Steps 2

3. IBIS Interconnect Task Group Meets Wednesdays 8AM PDT http://www.eda.org/ibis/interconnect_wip/ Major Contributors Altera Cadence Design Systems Intel Corp Keysight Technologies Mentor Graphics Micron Technology Signal Integrity Software Synopsys Teraspeed Labs David Banas Bradley Brim Michael Mirmak Radek Biernacki Arpad Muranyi Justin Butterfield, Randy Wolff Walter Katz Rita Horner Bob Ross 3

4. Models Represent Package and On-Die Interconnect Languages Supported IBIS-ISS Touchstone Model Terminals Pins Die Pads Buffer Signals Buffer Supplies 4

5. On Die, Package, Supply and Signal Interconnect can be Combines or Kept Separate Supports separate on-die and package interconnect models and combined on-die and package interconnect models Independent Supply and Signal Interconnect Models Coupled Supply and Signal Interconnect Models Singled Ended and Differential Interconnect Models 5

6. Similar Approach for Both IBIS and EBD IBIS (.ibs) Interconnect Model Terminals Pins ([Pins]) Die Pads Buffers EBD (.ebd) Interconnect Model Terminals Pins ([Pin List]) reference_designator.pin EBD will be a separate BIRD based on the IBIS package BIRD when completed EBD will be updated as soon as .ibs package BIRD is Finished 6

7. IBIS Interconnect Model Terminals Pins Die Pads Signal (I/O) Supply (POWER and GND) Buffers Signal (I/O) Supply Pullup Reference Pulldown Reference Power Clamp Reference Ground Clamp Reference External Reference 7

8. Interconnect Model Terminals Terminal <terminal number> Pin|DiePad|Buffer One line per terminal Supports both Pre and Post Layout Example Terminal records Terminal 1 Pin Pin_name M8 Terminal 2 Pad Pin_name M8 Terminal 3 Buffer Pin_name M8 Terminal 4 Buffer Pin_name M8 Pullup_Reference Terminal 5 Pin Model_name DQ Terminal 6 Pin Model_name DQS Diff_pos Terminal 8 Pin Model name DQ SE Terminal 9 Buffer Pin_name M9 Aggressor Terminal 10 Buffer Pin_name M10 Victim Terminal 11 Buffer Signal_name VDDQ 8

9. Pre and Post Layout IBIS Files Post Layout Signal (I/O) Terminals Pin, Die Pad and Buffer terminals referenced by Pin_name Supply Terminals Pin terminals referenced by Pin_name or Signal_name Die Pad terminals referenced by Die_Pad_name or Signal_name Buffer terminals referenced by Pin_name or Signal_name Pre Layout Signal (I/O) Terminals Referenced by Model_name Supply Terminals Referenced by Signal_name 9

10. Corners File, Subckt and Parameters can have either a single value or three corner values It is not clear if we will have a clear definition of the three corners Typ, Min, Max Can be Typ, Slow, Fast Can be Typ, Small Crosstalk, Large Crosstalk Expect it will inherit the existing usage of Typ, Min and Max and will be up to EDA tool on how to apply these corners. 10