Machine Learning of Interconnect Coupling Delay and Transition Effects

This research paper explores the use of machine learning to study interconnect coupling delay and transition effects in VLSI design. It discusses the challenges of calibrating non-SI to SI timing reports, the impact of clock period adjustments on path slack, and the complexities involved in the calibration process. The study sheds light on divergence between non-SI and SI modes and provides insights into improving accuracy while saving costs and runtime.

• Machine Learning
• Interconnect Coupling
• VLSI Design
• SI Calibration
• Timing Reports

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1. SI for Free: Machine Learning of Interconnect Coupling Delay and Transition Effects Andrew B. Kahng , Mulong Luo , Siddhartha Nath ECE and CSE Departments, UC San Diego {abk, muluo, sinath}@ucsd.edu UCSD VLSICAD Laboratory 1

2. Outline Motivation Previous Work Our Methodology and Accuracy Results Design of Experiments and Robustness Results Conclusions UCSD VLSICAD Laboratory 2

3. Non-SI to SI Calibration Use Case Post P & R Database .sdc .sdc .v .spef .db, .lib .v Non-SI Timing Report Non-SI Timing Report Non-SI Timing Report Save cost Save runtime But still accurate Calibration: Recipe to Convert Non-SI Timing Report to SI Timing Report SI Timing Report SI Timing Report SI Timing Report UCSD VLSICAD Laboratory 3

4. Non-SI vs. SI: How Bad is the Divergence? Slack diverges by 81ps (clock period = 1.0ns) 81ps is ~4 stages of logic at 28nm FDSOI Ideal correlation Path Slack in Non-SI Mode (ns) 81ps Path slack in SI Mode (ns) UCSD VLSICAD Laboratory 4

5. Non-SI to SI Calibration is Difficult! Multiple electrical, logic structure and layout parameters Complex interactions between parameters Black-box code in STA tools Electrical parameters SI Timing reports: Incr delay Transition time Path delay Logic structure parameters Commercial STA tools Layout parameters UCSD VLSICAD Laboratory 5

6. Example Challenge: Clock Period Dependency path slack is 81ps at signoff clock period of 1.0ns Tightening clock period to 0.82ns changes path slack to 143ps! 0.15 143ps at tighter clock period Max Delta Path Slack (SI non-SI) (ns) 0.14 0.13 81ps at signoff clock period 0.12 0.11 0.1 0.09 0.08 0.07 0.06 0.96 0.98 1.27 1.29 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 0.97 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 1.26 1.28 1.30 Clock period (ns) UCSD VLSICAD Laboratory 6

7. Example Challenge: Ground Capacitance Dependency 0.16 14ps 0.14 0.12 Arc Timing (ns) 15ps 0.1 DTran 0.08 SI Incr Delay 0.06 Non-SI Incr Delay 0.04 0.02 0 0.004 0.006 0.008 0.01 0.012 0.014 Ground Capacitance (pF) Incremental transition time (DTran) increases but incremental delay (SI Incr Delay) due to SI decreases This anti-correlation is non-obvious! UCSD VLSICAD Laboratory 7

8. Our Contributions Identify multiple sources of timing divergence between non-SI and SI modes Provide new insights in terms of modeling parameters required to calibrate non-SI to SI timing Develop new models to calibrate non-SI to SI timing using machine learning-based techniques Demonstrate accuracy and robustness of our models on a variety of testcases Worst-case divergence of 5.2ps in incremental delay due to SI Worst-case divergence of 8.2ps in SI-aware path delay UCSD VLSICAD Laboratory 8

9. Outline Motivation Previous Work Our Methodology and Accuracy Results Design of Experiments and Robustness Results Conclusions UCSD VLSICAD Laboratory 9

10. Review of Previous Works Analytical SI-induced delay models Sapatnekar2000 Lumps coupling capacitance to ground capacitance using Miller coupling factors Uses an iterative algorithm to estimate crosstalk delay on nets Xiao2000 Derive a two-pole model for crosstalk noise computation using iterative Newton- Raphson method Correlation of STA tools Thiel2004 Correlate SPICE to PT timing reports Kahng2013 Propose an offset-based correlation and wire delay estimation using linear regression to calibrate path slacks with PT Han2014 Develop machine learning models to correlate SI to SI and non-SI to non-SI timing between STA tools, and STA and design implementation tools UCSD VLSICAD Laboratory 10

11. Miscorrelations of Han2014 Calibrate non-SI to non-SI or SI to SI Signoff timer to signoff timer Signoff timer to IC implementation tools Divergence of 60ps when trying to calibrate non-SI to SI We need new models to calibrate SI from non-SI! Predicted Incremental Delay in SI Mode using non-SI Mode Information (ps) Ideal correlation 60ps Actual Incremental Delay in SI Mode (ps) UCSD VLSICAD Laboratory 11

12. Outline Motivation Previous Work Our Methodology and Accuracy Results Design of Experiments and Robustness Results Conclusions UCSD VLSICAD Laboratory 12

13. Identifying Modeling Parameters Incremental Delay in SI Mode (ns) Incremental Delay in SI Mode (ns) LE Rw x Cc Need to consider new electrical parameters Rw is the resistance of an arc Cc is the coupling capacitance of an arc LE is the logic effort of a driver Thus, RW, Cc, LE have great impacts on timing, we identify them as parameters for incremental delay in SI mode UCSD VLSICAD Laboratory 13

14. List of Modeling Parameters Modeling Parameters Type Source Transition time in non-SI mode Electrical Non-SI timing reports Resistance of an arc Electrical SPEF Coupling cap of an arc Electrical, layout SPEF Ratio of coupling to total capacitance Electrical, layout SPEF Logical effort of driver Electrical SPEF, Liberty Ratio of arc s stage to total # stages Logic structure Non-SI timing reports Clock period Several new electrical, logic structure, layout parameters Constraint SDC {Min, max} x {rise, fall} delta arrival times between the worst aggressor and victim Electrical Non-SI timing reports Toggle rate of victim net Operational, logic structure Non-SI timing reports Path delay in non-SI mode Electrical Non-SI timing reports Incremental transition time due to SI Incremental delay due to SI SI-aware path delay Electrical, logic structure, and layout parameters and constraint UCSD VLSICAD Laboratory 14

15. Comparison between Models Predicted Path Delay (ps) Predicted Path Delay (ps) Ideal correlation 87.3ps 8.2ps Ideal correlation Actual Path Delay (ps) Actual Path Delay (ps) Han2014 models have worst-case path delay error of 87.3ps vs. 8.2ps error from our models UCSD VLSICAD Laboratory 15

16. Modeling Flow Timing Reports in SI Mode Timing Reports in Non-SI Mode Create Training, Validation and Testing Sets ANN (2 Hidden Layers, 5-Fold Cross-Validation) SVM (RBF Kernel, 5-Fold Cross-Validation) HSM (Weighted Predictions from ANN and SVM) Save Model and Exit Linear regression cannot capture complex interactions between parameters Non-linear techniques capture these interactions using hidden parameters UCSD VLSICAD Laboratory 16

17. Incremental Transition Time (Due to SI) Model ???= ? ??? ,??,??,???,????,????,?? Incremental Transition Time (Due to SI): Transition Time considering SI Transition Time w/o SI We use six modeling parameters Meaning Incremental transition time of an arc due to SI Transition time of an arc in non-SI mode Resistance of an arc Coupling capacitance of an arc Ratio of coupling to total capacitance Clock period Logical effort of the driver of the net UCSD VLSICAD Laboratory 17

18. Accuracy of Incremental Transition Time Prediction Predicted Incremental Transition Time (ps) Ideal correlation 7.0ps Actual Incremental Transition Time (ps) Worst-case absolute error of 7.0ps (8.8%) Range of errors is 11.3ps Average absolute error of 0.7ps (0.6%) UCSD VLSICAD Laboratory 18

19. Incremental Delay (Due to SI) Model ???= ? ??? , ???,??,??,???,????,??,????, ????, ??????,(?,?), ??????,(?,?),??,?? Incremental Delay (Due to SI): Delay considering SI Delay w/o SI We use 11 modeling parameters Meaning Incremental delay of an arc due to SI Incremental delay of an arc in non-SI mode Incremental transition time of an arc due to SI (predicted) Resistance of an arc Coupling capacitance of an arc Ratio of coupling to total capacitance Ratio of arc s stage to total # stages Clock period Delta of min (rise, fall) arrival time between aggressor and victim Delta of max (rise, fall) arrival time between aggressor and victim Toggle rate of net Logical effort of the driver of the net UCSD VLSICAD Laboratory 19

20. Accuracy of Incremental Delay Prediction Ideal correlation Predicted SI Incr Delay (ps) 5.2ps Actual SI Incr Delay (ps) Worst-case absolute error of 5.2ps (15.7%) Range of errors is 9.8ps Average absolute error of 1.2ps (1.1%) UCSD VLSICAD Laboratory 20

21. SI-Aware Path Delay Model ???? ???= ? ??? , ???,???? ?=1 We use three modeling parameters Meaning Difference in path delays in SI and non-SI modes Non-SI path delay across all timing arcs Sum of incremental delay due to SI (predicted) across all stages in a path Number of stages in a timing path UCSD VLSICAD Laboratory 21

22. Accuracy of Path Delay Prediction Ideal correlation Predicted Path Delay (ps) 8.2ps Actual Path Delay (ps) Worst-case absolute error of 8.2ps (6.9%) Average absolute error of 1.7ps (1.4%) UCSD VLSICAD Laboratory 22

23. Outline Motivation Previous Work Our Methodology and Accuracy Results Design of Experiments and Robustness Results Conclusions UCSD VLSICAD Laboratory 23

24. Testcases We use real open-source designs and artificial testcases Technology: 28nm foundry FDSOI Total data points: 188K Testcase Type Testcase Name Source Signoff Clock Period (ns) #Instances at Post-Synthesis CPU OST2 (1-core) Oracle (formerly, Sun) 2.2 350K GPU THEIA OpenCores 2.0 125K Modem Viterbi OpenCores 1.0 97K Encoder JPEG OpenCores 0.8 62K Crypto AES OpenCores 1.0 13K Stack FIFO Designware 0.75 6.5K Artificial ART UCSD 1.0 >= 100 UCSD VLSICAD Laboratory 24

25. Artificial Testcases Clock periods: tight (-200ps less than signoff period) and loose (200ps more than signoff period) #Stages in artificial testcase: {15, 20, 25, 30} Miller coupling factor (MCF): {2, 1, 0} RC scaling factors: {0.5, 1.0, 2.0} Driver sizes in artificial: {X6, X16, X24, X32} UCSD VLSICAD Laboratory 25

26. STA Tool Flows Read databases of timing libraries Read and link design (post-P&R netlist) Read constraints (.sdc) and parasitics (.spef) In non-SI mode, use MCF to add coupling cap to ground cap In SI mode, set flags to not reselect critical path for SI analysis, select clock nets and delay analysis mode as edge-aligned Perform path-based timing analysis of top-1K paths Obtain detailed timing reports UCSD VLSICAD Laboratory 26

27. Robustness of Models Ideal correlation Predicted SI Incr Delay (ps) 7.9ps Actual SI Incr Delay (ps) New implementation of JPEG has different clock period, #stages, utilization Worst-case absolute error of 7.9ps (12.3%) Average absolute error of 1.6ps (2.6%) UCSD VLSICAD Laboratory 27

28. Outline Motivation Previous Work Our Methodology and Accuracy Results Design of Experiments and Robustness Results Conclusions UCSD VLSICAD Laboratory 28

29. Conclusions Calibration of non-SI to SI enables cost and runtime savings for SoC design teams We analyze electrical, logic structure and layout parameters that cause timing divergence between non-SI and SI modes We develop machine learning-based models to accurately calibrate non-SI to SI timing Our models have a worst-case error of 8.2ps Si-aware path delay in a 28nm foundry FDSOI technology Ongoing Correlate graph-based and path-based timing analysis Integrate our models with an academic timer THANK YOU!!! Our thanks to Dr. Tuck-Boon Chan of Qualcomm Inc. and Ms. Nancy MacDonald of Broadcom Corp. UCSD VLSICAD Laboratory 29

30. BACKUP UCSD VLSICAD Laboratory 30

31. Han2014 Modeling Parameters Transition Time Wire delay ?? wire delay ???,?,? cell output transition time Rw wire resistance C?, ????, ?????, wire, effective, coupling capacitance UCSD VLSICAD Laboratory 31

32. Why Bother About SI vs. Non-SI Calibration? Calibration: Conversion of a Non-SI timing report to SI timing report Many tools perform static timing analysis (STA) in both signal integrity (SI) mode and non-SI mode Cost differences STA tool with SI mode: expensive STA tool without SI mode: cheap Runtime differences For a design with 110K instances, exhaustive path-based analysis runtime of SI is 3 the runtime of non-SI Question: Should design team buy SI licenses or cheaper non-SI licenses? UCSD VLSICAD Laboratory 32