Digital Logic Design with Alex Bronstein
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Alex Bronstein
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Learn how to design logic systems
Learn the design of a simple CPU (MIPS)
Stop worrying and learn to love digital systems
S
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:
B.Sc. and M.Sc. in EE, Technion (1998-2005)
Ph.D. in CS, Technion (2005-2007)
Prof., EE@Tel Aviv University (2010-2016)
Prof., CS@Technion (from 2016)
Research interests: computer vision, machine learning, computational
geometry, imaging and image processing
I
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:
Cofounder and VP Technology, Novafora Inc. (2006-2009)
Cofounder, Invision Ltd. (2009-2012)
Research Scientist & Principal Engineer, Intel Corporation (from 2012)
Cofounder and Chief Scientist, Videocites Ltd. (from 2014)
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:
25% home assignments
75% final exam
A
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:
2 “dry” exercises (2.5%)
2
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Passing grade (>54) mandatory in each of the “wet” exercises
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F
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(
A
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)
Design specs
Architecture
RTL design
Functional verification
Logic synthesis
Floor planning
Placement & routing
Physical verification
Tapeout
Mask tooling
Fabrication
Packaging
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F
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Technology
library
Static timing analysis
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l
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(
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Design specs
Architecture
RTL design
Functional verification
Logic synthesis
Placement & routing
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Design specs
Architecture
High-level code
Compilation
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H
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w
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Design cost
Low
High
Design cycle
Fast
Slow
Language
High-level languages
HDL
(Java, C#, C++, C)
(Verilog, VHDL)
Code undergoes
Compilation
Synthesis
Parallelism
Usually sequential
Inherently parallel
(SIMD, threading, IPC)
Target platforms
CPU
FPGA or ASIC
(x86,ARM,GPU,DSP)
(lots of processes)
G
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d
E
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g
P
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s
M
o
d
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l
a
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t
y
Design basic building blocks (modules)
Connect modules together to form another module
A module can be replaced by a new version without affecting the rest
of the system
S
t
a
n
d
a
r
d
i
z
a
t
i
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n
Using a library with a small amount of standard modules
Clearly defined functionality and interfaces
Don’t reinvent the wheel
A
b
s
t
r
a
c
t
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o
n
Decomposition of design process into a hierarchy of levels
Hide unnecessary lower-level details
A
b
s
t
r
a
c
t
i
o
n
Simplifies design and understanding of complex systems
A higher level of abstraction is based on the level beneath
A higher level of abstraction hides details of lower levels
Always try to solve problems at the highest possible level of abstraction
Example of abstraction hierarchy:
High-level language
Machine language
Register-transfer level (RTL)
Gate level, analog electronics
Physics
A
b
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r
a
c
t
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n
v
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.
I
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A
b
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:
l
o
w
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v
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h
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h
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r
l
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v
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I
m
p
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t
a
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i
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n
:
h
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g
h
l
e
v
e
l
l
o
w
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r
l
e
v
e
l
Abstraction requires adhering to a certain set of rules to be valid
High-level language:
variable
Register-transfer level:
register
Gate level:
NAND gates
Physics:
p-type and n-type MOSFETs
A
b
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D
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L
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Input:
V
in
> V
IH
1
Output:
V
out
> V
OH
1
Input:
V
in
< V
IL
0
Output:
V
out
< V
OL
0
V
IL
< V < V
IH
undefined
N
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m
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Allows modularity!
V
IH
V
OH
V
OL
V
IL
noise
margin
noise
margin
V
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(
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–
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P
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(
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–
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d
V
IH
V
IL
V
in
t
V
OH
V
OL
V
out
t
t
CD
t
CD
t
PD
t
PD
C
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b
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a
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L
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(
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=
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p
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t
B
u
i
l
d
i
n
g
b
l
o
c
k
s
:
Logic gates
Wires
Combinational logic sub-systems
B
u
i
l
d
i
n
g
r
u
l
e
s
:
No feedback
No floating wires (except inputs and outputs)
N
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t
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,
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a
r
e
a
l
s
o
v
a
l
i
d
a
n
d
s
t
a
b
l
e
Allows resilience to inaccurate analog components
Prevents noise accumulation during signal propagation
A
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w
s
c
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a
p
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a
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s
p
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t
s
OLD
NEW, Stable
OLD
NEW, Stable
OLD
NEW, Stable
INPUT
OUTPUT
1
OUTPUT
2
S
t
a
t
i
c
T
i
m
i
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g
E
x
a
m
p
l
e
:
I
n
v
e
r
t
e
r
(
N
O
T
g
a
t
e
)
V
in
< V
IL
V
out
> V
OH
V
in
> V
IH
V
out
< V
OL
V
OH
V
OL
V
out
V
IL
V
IH
V
in
Actual components have different
analog characteristics due to
Fabrication tolerances
Temperature changes
Supply voltage fluctuations
S
t
a
t
i
c
T
i
m
i
n
g
C
o
n
t
a
m
i
n
a
t
i
o
n
d
e
l
a
y
(
t
C
D
)
–
m
i
n
i
m
u
m
t
i
m
e
f
o
l
l
o
w
i
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g
i
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p
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w
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v
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o
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p
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s
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g
u
a
r
a
n
t
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e
d
Components in parallel:
min of t
CD
Components in series:
sum of t
CD
P
r
o
p
a
g
a
t
i
o
n
d
e
l
a
y
(
t
P
D
)
–
m
a
x
i
m
u
m
t
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m
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f
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l
o
w
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w
o
u
t
p
u
t
i
s
g
u
a
r
a
n
t
e
e
d
Components in parallel:
max of t
PD
Components in series:
sum of t
PD
S
y
n
c
h
r
o
n
o
u
s
S
t
a
t
i
c
M
e
m
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P
o
s
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v
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d
g
e
-
t
r
i
g
g
e
r
e
d
D
f
l
i
p
-
f
l
o
p
(
D
F
F
)
L
o
g
i
c
a
l
c
h
a
r
a
c
t
e
r
i
s
t
i
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:
Output Q assumes the value of D after CLK rise
T
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g
c
h
a
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t
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r
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t
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:
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f
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p
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d
t
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a
f
t
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c
l
o
c
k
r
i
s
e
t
h
e
n
old output will stay valid at least t
cCQ
and new output will become valid
at most t
pCQ
after clock rise
NEW
OLD
NEW
CLK
D
Q
t
SU
t
H
t
cCQ
t
pCQ
S
y
n
c
h
r
o
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o
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s
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t
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M
e
m
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S
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c
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s
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e
q
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t
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m
a
c
h
i
n
e
s
B
u
i
l
d
i
n
g
b
l
o
c
k
s
:
Combinational logic modules
Clocked memory modules
Wires
B
u
i
l
d
i
n
g
r
u
l
e
s
:
No CL loops unless through at least one memory module
Clock period long enough to satisfy timing requirements
All inputs remain stable enough time to satisfy timing requirements
F
i
n
i
t
e
S
t
a
t
e
M
a
c
h
i
n
e
s
(
F
S
M
)
C
L
U
1
U
n
…
Y
1
Y
m
…
X
1
X
k
…
X’
1
X’
k
…
M
E
M
O
R
Y
I
N
P
U
T
S
O
U
T
P
U
T
S
P
R
E
S
E
N
T
S
T
A
T
E
N
E
X
T
S
T
A
T
E
A finite set of states X
{0,…,K-1}k bits represent 2
k
states
n-bit input U
m-bit output Y
S
t
a
t
e
u
p
d
a
t
e
f
u
n
c
t
i
o
n
:
X[t+1] =
(X[t],U[t])
O
u
t
p
u
t
f
u
n
c
t
i
o
n
:
Mealy FSM:
Y[t] =
(X[t],U[t])
Moore FSM:
Y[t] =
(X[t])
F
S
M
T
i
m
i
n
g
C
L
U
Y
X
X’
D
F
F
s
CLK
t
pCQ
t
PD
t
SU
C
l
o
c
k
p
e
r
i
o
d
T
>
t
p
C
Q
+
t
P
D
+
t
S
U
F
S
M
T
i
m
i
n
g
C
L
U
Y
X
X’
D
F
F
s
CLK
t
PD
t
SU
C
l
o
c
k
p
e
r
i
o
d
T
>
t
p
C
Q
+
t
P
D
+
t
S
U
I
n
p
u
t
s
e
t
u
p
t
i
m
e
t
S
U
(
U
)
>
t
P
D
(
C
L
)
+
t
S
U
F
S
M
T
i
m
i
n
g
C
L
U
Y
X
X’
D
F
F
s
CLK
C
l
o
c
k
p
e
r
i
o
d
T
>
t
p
C
Q
+
t
P
D
+
t
S
U
I
n
p
u
t
s
e
t
u
p
t
i
m
e
t
S
U
(
U
)
>
t
P
D
(
C
L
)
+
t
S
U
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n
p
u
t
h
o
l
d
t
i
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e
t
H
(
U
)
>
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In this course, delve into digital logic design concepts with Alex Bronstein. Explore the fundamentals of designing logic systems and learn the intricacies of a simple CPU design. Gain insights into the world of digital systems and their applications. The course covers a range of topics from hardware design to formalities such as assignments and examinations. Meet the course staff responsible for guiding you through this educational journey. Discover the hardware design flow, including ASIC and FPGA technologies, and various stages in the design process. Embrace the opportunity to enhance your knowledge in digital logic design under the mentorship of experienced professionals.
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Presentation Transcript
1 Digital Logic Design 234262 Alex Bronstein
2 Computers Around Us
3 Course Goals Learn how to design logic systems Learn the design of a simple CPU (MIPS) Stop worrying and learn to love digital systems
4 Short bio In the Academia: B.Sc. and M.Sc. in EE, Technion (1998-2005) Ph.D. in CS, Technion (2005-2007) Prof., EE@Tel Aviv University (2010-2016) Prof., CS@Technion (from 2016) Research interests: computer vision, machine learning, computational geometry, imaging and image processing In the Industry: Cofounder and VP Technology, Novafora Inc. (2006-2009) Cofounder, Invision Ltd. (2009-2012) Research Scientist & Principal Engineer, Intel Corporation (from 2012) Cofounder and Chief Scientist, Videocites Ltd. (from 2014)
5 Course Staff Alex Bronstein (lecturer in charge) Taub 719 bron@cs.technion.ac.il Chaim Baskin (lecturer) Taub 700 chaimbaskin@cs.technio.ac.il Noam Yeffet (TA in charge) Taub 327 snyefet@cs.technion.ac.il Tommy Bojan (TA) Taub 717 tommy.Bojan@intel.com Alon Gueta (TA) Taub TBD alon.gueta@campus.technion.ac.il Aviram Imber (TA) Taub 213 aviram.imber@campus.technion.ac.il Bahjat Kawar (TA) Taub 213 bahjat.kawar@campus.technion.ac.il Moshe Liechtenstein (TA) Taub 437 smosesli@cs.technion.ac.il
6 Course Formalities Grade: 25% home assignments 75% final exam Assignments: 2 dry exercises (2.5%) 2 wet Verilog coding exercises (10% each) Passing grade (>54) mandatory in each of the wet exercises
7 Hardware
8 Hardware
9 Hardware
10 Hardware Design Flow (ASIC) Technology library Tapeout Design specs Physical verification Mask tooling Architecture Static timing analysis RTL design Fabrication Functional verification Placement & routing Packaging Logic synthesis Floor planning Foundry Frontend Backend
11 Hardware Design Flow (FPGA) Design specs Architecture RTL design Functional verification Logic synthesis Placement & routing
12 Software Design Flow Design specs Architecture High-level code Compilation
13 Software vs. Hardware Software Hardware Design cost Low High Design cycle Fast Slow Language High-level languages HDL (Java, C#, C++, C) (Verilog, VHDL) Code undergoes Compilation Synthesis Parallelism Usually sequential Inherently parallel (SIMD, threading, IPC) Target platforms CPU FPGA or ASIC (x86,ARM,GPU,DSP) (lots of processes)
14 Good Engineering Practices Modularity Design basic building blocks (modules) Connect modules together to form another module A module can be replaced by a new version without affecting the rest of the system Standardization Using a library with a small amount of standard modules Clearly defined functionality and interfaces Don t reinvent the wheel Abstraction Decomposition of design process into a hierarchy of levels Hide unnecessary lower-level details
15 Abstraction Simplifies design and understanding of complex systems A higher level of abstraction is based on the level beneath A higher level of abstraction hides details of lower levels Always try to solve problems at the highest possible level of abstraction Example of abstraction hierarchy: High-level language Machine language Register-transfer level (RTL) Gate level, analog electronics Physics
16 Abstraction vs. Implementation Abstraction: low level higher level Implementation: high level lower level Abstraction requires adhering to a certain set of rules to be valid High-level language: variable Register-transfer level: register Gate level: NAND gates Physics: p-type and n-type MOSFETs
17 Abstraction of Digital Systems Physical Logical V Input: Vin > VIH 1 Output: Vout > VOH Input: 1 Vin < VIL 0 VOH noise margin Output: Vout < VOL VIL < V < VIH 0 VIH undefined VIL noise margin Noise margins increase robustness to noise VOL added to signal passing from the output of one component to the input of another Allows modularity!
18 Timing Contamination delay (tCD) minimum time following input change during which validity of previous output is guaranteed Propagation delay (tPD) maximum time following input change after which the validity of new output is guaranteed Vin VIH VIL t Vout tPD tPD VOH VOL t tCD tCD
19 Combinational Logic (CL) Output = Boolean function of the input Building blocks: Logic gates Wires Combinational logic sub-systems Building rules: No feedback No floating wires (except inputs and outputs) Number of inputs each output drives does not exceed fanout limitations
20 Static Timing If inputs to CL system are valid and stable, after settling time, outputs are also valid and stable INPUT OLD NEW, Stable OUTPUT1 OLD NEW, Stable OUTPUT2 OLD NEW, Stable Allows resilience to inaccurate analog components Prevents noise accumulation during signal propagation Allows cheap mass production of components
21 Static Timing Example: Inverter (NOT gate) Vin < VIL Vin > VIH Vout > VOH Vout < VOL Vout VOH Actual components have different analog characteristics due to Fabrication tolerances Temperature changes VOL Supply voltage fluctuations Vin VIL VIH
22 Static Timing Contamination delay (tCD) minimum time following input change during which validity of all previous outputs is guaranteed Components in parallel: min of tCD Components in series: sum of tCD Propagation delay (tPD) maximum time following input change after which the validity of all new output is guaranteed Components in parallel: max of tPD Components in series: sum of tPD
23 Synchronous Static Memory Positive edge-triggered D flip-flop (DFF) D Q CLK Logical characteristic: Output Q assumes the value of D after CLK rise Timing characteristic: CLK If input is held constant tSU before and tH after clock rise then old output will stay valid at least tcCQ and new output will become valid tSUtH D NEW tcCQ Q OLD NEW tpCQ at most tpCQ after clock rise
24 Synchronous Static Memory
25 Synchronous Sequential Logic State machines CL Building blocks: Combinational logic modules Q D Clocked memory modules CLK Wires Building rules: No CL loops unless through at least one memory module Clock period long enough to satisfy timing requirements All inputs remain stable enough time to satisfy timing requirements
26 Finite State Machines (FSM) A finite set of states X {0, ,K-1} U1 Y1 k bits represent 2k states INPUTS OUTPUTS Un Ym n-bit input U CL X1 X 1 m-bit output Y PRESENT STATE NEXT STATE Xk X k State update function: X[t+1] = (X[t],U[t]) MEMORY Output function: Mealy FSM: Y[t] = (X[t],U[t]) Moore FSM: Y[t] = (X[t])
27 FSM Timing Clock period T > tpCQ + tPD + tSU U Y CL X X tPD DFFs tpCQ tSU CLK
28 FSM Timing Clock period T > tpCQ + tPD + tSU U Y CL Input setup time X X tPD tSU(U) > tPD(CL) + tSU DFFs tSU CLK
29 FSM Timing Clock period T > tpCQ + tPD + tSU U Y CL Input setup time X X tSU(U) > tPD(CL) + tSU Input hold time tH(U) > tH(DFF)- tCD(CL) DFFs CLK
30 Additional Timing Considerations Clock skew: clock signal arrives Q D Q D Q D with different delay to different CLK CLK CLK memories Clock jitter: clock is not exactly periodic Asynchronous inputs may violate hold requirement and cause metastability
31 Latency and Throughput Latency: amount of time passing between the beginning of a calculation and its end (input-to-output delay) Throughput: rate at which calculations are performed (=calculations per unit of time)
32 Latency and Throughput Example: sum of N numbers MEM Sequential implementation Latency Throughput = N t0 = 1/(N t0) Combinational implementation Latency = log2N t0 Throughput = 1/(log2N t0)
