Pixel Array Status and Drawing Rules for High-Resistivity Epi Design
This collection of images and descriptions provides an overview of the pixel array status as of April 26, 2019, along with drawing rules for high-resistivity epi design. The pixel array features various components such as Pixel_S1, Pixel_S3, and the overall array structure. Drawing rules highlight the requirements for marking layers and guard rings in the design. Detailed recommendations are given for the configuration of the pixel array guard ring.
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Presentation Transcript
Pixel Array Status 2019.4.26
Pixel_S1 DRC LVS
Pixel_S3 DRC LVS
Pixel array DRC LVS 4*48*512 pixel Pitch 26,26,23.11,26um 26um Aout M3 sector M5&M4
Drawing rules DEV_AREA(hr) high-res Marking layer for High-Resistivity Epi design DEV_AREA(hr) marking layer must cover the entire chip area, including pads, seal ring, etc DEV_AREA(gg) Marking Layer for Pixel Array Guard Ring High-Resistivity EPI design must contain pixel array guard ring marking layer : DEV_AREA(gg) AREA10(cy) cis-array ARRAY_AREA=80dt72 layer is used to define the pixels area for DRC, LVS and MDP. Outside ARRAY_AREA, TS18SL rules are applicable.
Drawing rules WPD (Deep P-Well) must cover the whole CMOS Area, excluding: Deep N-Wells (WB) A fixed distance of 1 [um] between WPD to any WB must be kept Pixel ARRAY_AREA (80dt72) Pixel Array N-Well Guard Ring (77dt106)
Pixel array guard ring Triple Guard Ring Recommendation
