Cutting-Edge Interconnect Technology for High-Performance Computing

Explore the world of high-performance embedded computing through images and descriptions detailing key components like terrestrial autonomous vehicles, wireless infrastructure, FPGA-based data exchange, and more. The content dives into fault tolerance, data processing, redundant computing, and hardware configurations critical for next-gen applications like autonomous vehicles and advanced RADAR systems.

• Interconnect Technology
• High Performance Computing
• Autonomous Vehicles
• FPGA Processing
• Data Switching

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Uploaded on Sep 27, 2024 | 0 Views

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1. Interconnect Technology for High Performance Embedded Computing (HPEC) 1 9/27/2024

2. 2 9/27/2024

3. Terrestrial autonomous vehicles Big science (SKA, LHC) RADAR UAVs 5G infrastructure 3 9/27/2024

4. Results are time critical Fault tolerance is required Size Weight and Power (SWaP) constrained Wireless infrastructure RADAR Processing Autonomous Vehicles 4 9/27/2024

5. Up to 1024 channels Channels exchange data via RapidIO switches embedded in Intel Arria 10 FPGAs 5 9/27/2024

6. Redundant general-purpose computing for prediction, tracking, motion planning sensor data preprocess with either FPGA or dedicated ASSP ML based process for perception and other tasks typically uses some high-end AI accelerator such as GPGPU high bandwidth low latency data switch for sensor and localization data piping to processing and storage Deterministic, high-reliability data switch for command and control of the vehicle platform Large shared memory for frame buffer and other high throughput data sharing between different processor nodes Clearly problematic for an electric vehicle 6 9/27/2024

7. Copper vs Fiber Cabling vs Backplane 7 9/27/2024

8. Space wire and Space Fiber Automotive network protocols: LIN, CAN, MOST and FlexRay. 8 9/27/2024

9. Up to 256 ports Multi-terabit switching bandwidth with HBM memory support Memory Mapped (MM) SoC bridges for shared memory computing Streaming bridges for hardware processing via HLS kernels NIC for Ethernet traffic 9 9/27/2024

10. 112G PAM4 transceivers Up to 32 GB of HBM memory Over 6 Tbps of memory bandwidth Up to 5.6 Million programmable logic cells 24 x 100 Gb Fusion ports Capable of mapping up to 5 PB of shared memory 10 9/27/2024

11. 11 9/27/2024

12. 12 9/27/2024