Overview of DARE22 Test Vehicle Design on FD SOI 22nm Process

This detailed presentation explores the test structures and components inside the TV, including combinatorial logic, sequential logic, clock gating, ring oscillators, input-output cells, analog IPs, and more. It covers various test scenarios such as irradiation testing, SET/SEU measurements, functional verifications, leakage vs. TID comparisons, and more. The sensitive area at the RADEF facility, beam flux, required fluence, strikes on active devices, and beam duration are also discussed. In addition, the combinatorial logic section delves into selected cells for radiation testing and their respective specifications.

• Test Structures
• Radiation Testing
• Combinatorial Logic
• Analog IPs
• Sequential Logic

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1. DARE22 TEST VEHICLE DESIGN ON FD SOI 22NM PROCESS LAURENT BERTI

2. OUTLINE Test structures overview Logic combinatorial Logic sequential Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs 2

3. TEST STRUCTURES OVERVIEW : WHAT INSIDE THE TV ? WHICH TESTS ? Irradiation test TID SET Structure Measurements SEE SEU SEL Combinatorial logic Functional verification + SET cross section versus LET + SET duration + leakage vs TID Clock gating Functional verification + SET/SEU cross section versus LET + leakage vs TID Sequential logic Functional verification + SEU cross section versus LET of standard and DICE FFP + leakage vs TID Ring oscillators Frequency (delay) versus TID IOs Characterization + ESD + performances versus TID + SET cross section Analog IP Characterization + performances versus TID + SEE cross section DPRAM (commercial) Functional verification vs TID + SEU cross section versus LET of the standard DPRAM + leakage vs TID 3

4. SENSITIVE AREA : RADEF FACILITY Standard beam flux 20k ions/(s.cm2) Max. fluence required: 1e7 ions/cm2 Min. strikes on active devices: 100 SA = # events / fluence = 100 /1e7 = 1000 m2 Beam duration: 500 s 4

5. OUTLINE Test structures overview Combinatorial logic Sequential logic Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 5

6. COMBINATORIAL LOGIC: SELECTED CELLS FOR THE RADIATION Cells Number of cells version to be tested 48 Number of devices per flavor to achieve SA = 1000 m2 Total area mm2 CLKINVD1/4/8/16 11384/2816/1536/704 0.155 EXNORD1 NAND2D1/2/4 NAND3D1/2/4 NOR2D1/2/4 NOR3D1/2/4 FILT60M TMV 12 36 36 36 36 12 12 1792 0.041 0.203 0.195 0.176 0.175 0.051 0.024 > 1.919 18432/11264/5632 12288/7168/3584 16384/9216/4608 10240/5632/2816 768 384 Total area + layout margin 6

7. COMBINATORIAL LOGIC: SCAN AND SET TEST STRUCTURES Two configurations: Scan test (production test) Irradiation test (SET) 2 combiners CCELLs + delay cells (steps 10ps till 200ps, 20ps till 400ps and 50ps till 1ns) 7

8. COMBINATORIAL LOGIC Outputs read and latch reset every 5ms (by the SPI) Probability of double events during 5ms: ? ? = 2,5?? = ?? = 4.995 10 7 ?! Probability to have at least 1 double event during 500s ? ? = 2,500? = 1 [1 ? ? = 2,5?? ]500/0.005= 4.872% 8

9. OUTLINE Test structures overview Combinatorial logic Sequential logic Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 9

10. SEQUENTIAL LOGIC: SELECTED CELLS FOR THE RADIATION Due to the area limitation, only 5 flavors FF DICE implemented 4 Vths for 20 nm + 1 Vth (HVT) for 28 nm (slowest flavor) SA can be calculated only for standard D-FFs. The DICE area is estimated by: active device area = 10*SA(standard DFF) Only 50% of the SA initially targeted has been implemented The irradiation time will be doubled Cells Type FFP Area (mm2) SXDFFRLSLQD1 (SLVT, SVT, HVT, RVT) (20nm) DICE 5.7914 SXDFFRLSLQD1 (HVT) (28nm) DICE 1.4478 SDFFRLSLQD1 (12 flavors) standard 0.4238 Total area including layout margin 11.5 10

11. SEQUENTIAL LOGIC: SEU DETECTION SEU test configurations : pre-loaded data on a shift register Rad-hard clock buffering 6 configurations of tests : Data all 0, all 1 and checkerboard & Clk 0 and 1 11

12. OUTLINE Test structures overview Combinatorial logic Sequential logic Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 12

13. INTEGRATED CLOCK GATING: SELECTED CELLS FOR THE RADIATION EN STATE Q GCLK Latch TE CLK Integrated Clock Gating : mix between logic combinatorial and sequential Cells LETth Number of devices per flavor to achieve SA = 1000 m2 Area (mm2) (MeV.cm2/mg) 384 ICGS3 25 0.079 256 ICGS4 40 0.057 256 ICGS5 60 0.060 1152 ICGD4 non-hard 0.224 Total area including margin > 0.6 13

14. INTEGRATED CLOCK GATING: SET/SEU DETECTION Detect SET/SEU and their propagations through the chain SET SET SET SET SET SET SET SET 14

15. OUTLINE Test structures overview Logic combinatorial Logic sequential Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 15

16. RING OSCILLATORS (1GHZ) 16 oscillators : 12 different flavors of INV (same as used for logic_comb delay) + 2 flavors with NAND/NOR gates Monitoring oscillation frequency (gate delay) and consumption versus TID Output signal frequency is divided by 128 (7.8125 MHz) 16

17. OUTLINE Test structures overview Logic combinatorial Logic sequential Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 17

18. INPUT/OUTPUT IO CELLS All IOs will be characterized with and without TID irradiation (leakage, output I/V curves, delay...): PUL/PDN Schmitt trigger threshold level POC signal LVDS standard HIF test (SET/SEL) BD IOs LVDS (RX/TX) ESD test: robustness of the IOs 18

19. INPUT/OUTPUT CELLS : BIDIRECTIONAL SET DETECTION The SET detection at RX side is performed using 2 rad-hard latches, one for positive and the other for negative SET A SET filter is added at the latch output to remove latch SET 19

20. INPUT/OUTPUT CELLS : LVDS SET TESTS A loopback configuration between LVDS_RX and LVDS_TX is used during irradiation The SET detection is similar to the case of BD IOs : two hard-latches, and 2 RX for the TX discrimination 20

21. OUTLINE Test structures overview Logic combinatorial Logic sequential Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Back Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 21

22. ANALOG IPS : IVREF1V8 IVREF1V8 characterization with and without TID: Power-up and down consumptions References voltage/current versus tuning codes References voltage/current values versus temperature IVREF1V8 irradiation under HIF SET behavior (voltage variations) SEL robustness 22

23. IVREF1V8 : SET TEST CONFIGURATION Two fast comparators with 2 rad-hard latches, connected to VREF Threshold detection fixed externally (pin TI_SETVREF) 23

24. ANALOG IPS : PLL PLL characterization Power-up and down consumptions PLL frequency range: up to 3GHz (VCO frequency 2GHz-3GHz) Ultra low jitter (300 fs) PLL characterization under TID Power-up and down consumptions PLL frequency range vs TID dose (after the divider) PLL irradiation under HIF Detection of double edge SEL robustness 24

25. ANALOG IPS : PLL SET DETECTION 2 ways to provide the input clock reference (to reduce the jitter) Specific output buffer for the jitter characterization Divided PLL output signal (about 23MHz) to monitor SET 25

26. ANALOG IPS : BACK BIAS GENERATOR (BBG) & TID SENSOR Characterization with and without TID Power-up and down consumptions Body bias versus TID HIF irradiation SET behavior : Don t expect events, due to large filtering SEL robustness 26

27. OUTLINE Test structures overview Logic combinatorial Logic sequential Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 27

28. COMMERCIAL DPRAM (SYNOPSYS) Characterization with and without TID Power-up and down consumptions To investigate different memory cut sizes HIF irradiation To analyse the robustness of different DRAM configurations (different memory cut sizes) from SEU and MBU point of view Pre-load data, irradiate and after check data (static) Pre-load data, continuous reading and error counting during rradiation (dynamic) 28

29. OUTLINE Test structures overview Logic combinatorial Logic sequential Integrated clock gating (ICG) Ring oscillators Input output cells (Bidirectional IOs & LVDS) Analog IPs IVREF1V8 PLL Body Bias Generator (BBG) and TID sensor Commercial DPRAMs Digital Test Interface 29

30. DIGITAL TEST INTERFACE (DTI) The DTI uses a SPI protocol and register bank, to control/read all the tested blocks This DTI has been designed to be rad-hard using DICE D-FF and a rad-hard clock-trees with triplication DTI top level view TV top level view with DTI 30

31. CONCLUSION Characterization TID and SEE: Combinatorial logic Sequential logic Clock gating Ring oscillator IOs Commercial DPRAM IVREF PLL Back-bias generator & TID sensor Packaged dies expected early August 2022 Radiation measurements before the end of this year ACKNOWLEDGMENT The authors would like to thank the European Commission. This project (EFESOS) has been funded from the European Union s Horizon 2020 research and innovation programme. TV top layout (15 mm2) 31

32. 32 CONFIDENTIAL