Understanding Instruction Set Architecture and Data Types in Computer Systems
In computer architecture, the Instruction Set Architecture (ISA) level is crucial in defining how a processor executes instructions. This includes the formal defining documents, memory models, registers, and various data types that can be supported. The ISA level specifies the capabilities of a processor and influences the types of operations it can perform. Additionally, different architectures such as Intel's IA-32, ARM v7, and AVR 8-bit are discussed in terms of their implementations and usage in different devices. Furthermore, the content delves into data types supported by architectures, including numeric data types like signed and unsigned integers, floating-point numbers, and binary coded decimals, as well as non-numeric data types like characters, strings, and Boolean values.
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Instruction Set Architecture Level Ch 5.1, 5.2, 5.3 Darnit xkcd 2309
Instruction Set Architecture Level Ch 5.1, 5.2, 5.3
Instruction Set Architecture (ISA) level ISA level can be specified by a formal defining document Memory model Registers Data types Instructions Examples: Intel s IA-32, as embodied in the Core i7 Desktop machines and server farms ARM v7 architecture, implemented in the OMAP4430 system on a chip Phones, tablets, other mobile devices AVR 8-bit architecture, used by the ATmega168 microcontroller Low-end embedded systems such as traffic lights & clock radios 3
Data Types The Mic-1 architecture supports only one data type: 32 bit, two's complement integers. Since the hardware cannot be changed once it is built, any other data types desired would have to be done in software. The IJVM language has the following data types: 32 bit two's complement integers 16 bit two complement integers (e.g., branch displacements) 8 bit two complement integers (e.g., BIPUSH) The microcode converts all of these to 32 bit two's complement integers internally. The ISA can have data types not found on the hardware. However, for every data type the hardware supports, there is usually ISA level support as well. 4
Numeric Data Types Signed Integers: 8, 16, 32 and 64 bits (two's complement) Unsigned Integers: 8, 16, 32 and 64 bits Floating Point: single and double precision Binary Coded Decimal Often there will be separate registers for integer and floating-point numbers Core i7 OMAP 4430 ARM CPU ATmega168 AVR CPU Type 8 bits 16 bits 32 bits 64 bits 8 bits 16 bits 32 bits 64 bits 8 bits 16 bits 32 bits 64 bits Signed integer X X X X X X X X Unsigned integer X X X X X X X X X Binary coded decimal X Floating point X X X X 5
Non-Numeric Data Types Characters: ASCII (8 bits), UNICODE (16 bits) Strings: some ISA's have instructions for these, though the hardware will at best store characters Boolean value: need only one bit, sometimes use a bit map Pointers (i.e., machine address) Note that although the Mic-1 holds pointers in its registers, aside from when they are in the MAR or PC register and connected to the memory address lines, there is no hardware support for pointers. (they are added as if two's complement numbers) 6
Instruction Formats There are several possible formats for instructions, depending on the number of addresses (0, 1, 2, 3) present Approaches to instruction length All the same size Pro: easier decoding Con: wasted space (need to accommodate largest one) Varying size Shorter / same / longer than word length? 7
Considerations of instruction length Enough bits to sufficiently express all operations desired Short instructions are better than longer ones Reduces memory space Accommodate limited memory bandwidth The rate at which instructions can be executed may be limited by instruction length Let bandwidth of an instruction cache be t bps Let the average instruction length is r bits Then, the cache can deliver at most t/r instructions per second Number of bits in an address field Finer memory resolution longer addresses & longer instructions 8
Considerations of instruction length Enough bits to sufficiently express all operations desired Short instructions are better than longer ones Reduces memory space Accommodate limited memory bandwidth The rate at which instructions can be executed may be limited by instruction length Let bandwidth of an instruction cache be t bps Let the average instruction length is r bits Then, the cache can deliver at most t/r instructions per second Number of bits in an address field Finer memory resolution longer addresses & longer instructions 9
Expanding Op-codes (1) For a given instruction format length, there is a trade-off between the number of bits used for the op-code and the number used for the operands (e.g., addresses) More op-code bits more instructions More address bits more addressable locations By using specific prefixes of the op-code, we can get varying number of variable length op-codes Consider an (n+k) bit instruction with a k-bit opcode and a single n-bit address. This instruction allows 2? different operations and 2? addressable memory cells Alternatively, the same n+k bits could be broken up into a (k-1) bit opcode and an (n+1) bit address, meaning half as many instructions and either twice as much addressable memory or the same amount of memory with twice the resolution 10
Expanding Op-codes (2) Example: 15 instructions taking 3 addresses 14 instructions taking 2 addresses 31 instructions taking 1 address 16 instructions taking 0 addresses 11
Expanding Op-codes: Example Suppose we have 16 bit instruction lengths We want: 14 op-codes for instructions that take a 12-bit address 7 op-codes for instructions that will take a 10-bit address 8 op-codes for instructions that will take a 7-bit address 4 4- -bit opcodes (14): bit opcodes (14): 0000 aaaa aaaa aaaa 0001 aaaa aaaa aaaa 0010 aaaa aaaa aaaa 0011 aaaa aaaa aaaa 0100 aaaa aaaa aaaa 0101 aaaa aaaa aaaa 0110 aaaa aaaa aaaa 0111 aaaa aaaa aaaa 1000 aaaa aaaa aaaa 1001 aaaa aaaa aaaa 1010 aaaa aaaa aaaa 1011 aaaa aaaa aaaa 1100 aaaa aaaa aaaa 1101 aaaa aaaa aaaa 6 6- -bit opcodes (7): bit opcodes (7): 1110 00 aa aaaa aaaa 1110 01 aa aaaa aaaa 1110 10 aa aaaa aaaa 1110 11 aa aaaa aaaa 1111 00 aa aaaa aaaa 1111 01 aa aaaa aaaa 1111 10 aa aaaa aaaa 9 9- -bit op bit op- -codes (8): codes (8): 1111 1100 0 aaa aaaa 1111 1100 1 aaa aaaa 1111 1101 0 aaa aaaa 1111 1101 1 aaa aaaa 1111 1110 0 aaa aaaa 1111 1110 1 aaa aaaa 1111 1111 0 aaa aaaa 1111 1111 1 aaa aaaa 12
Expanding Op-codes: Example Consider the case of a processor with an instruction length of 12 bits and with 32 general-purpose registers, so the size of the address field is 5 bits. Is it possible to have instruction encodings satisfying all of the following? 3 two-address instructions 30 one-address instructions 45 zero-address instructions 13
