Monitoring and Power Supplies System Overview

This presentation showcases the monitoring and power supply system components including monitoring boards, interlock boards, Vidor boards, and populated PCBs. It also explains the functionality of these components, such as signal inputs and outputs, power connectors, and the simulation principles for avoiding unwanted interlocks. The system ensures proper monitoring and control of various parameters like temperature, humidity, pressure, and power supplies to maintain operational efficiency and safety.

• Monitoring
• Power Supplies
• System Components
• Interlock Boards
• Vidor Boards

suad_2 Follow

Uploaded on Sep 15, 2024 | 0 Views

Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

Presentation Transcript

1. MONITORING & POWER SUPPLIES

2. MONITORING & INTERLOCK CAEN_IT_board Vidor_board Monitoring_board ADC x8 TNTC x8 I2C ATOM Lite 1 T / Hum SHT85 I2C Interlock Power Supplies FPGA ADC x2 Press x2 I2C ATOM Lite 2 ALARM SOFT (to DCS) DCS ALARM HARD (to FPGA) INTERLOCK SIGNAL (if several successive ALARM HARD) 27/02/2024 - LPNHE - MARTIN and All

3. VIDOR BOARD Inputs signals : ALARM_T from 8 Temperature channels ALARM_H from 1 Humidity channel ALARM_P from 2 Pressure channel Logic Level 1=OK 0=nOK Outputs signals : IT30 to switch OFF the LP Supplies channels 3 to 0 IT47 to switch OFF the LP Supplies channels 7 to 4 Flexible point-to-point routing (red wires) 27/02/2024 - LPNHE - MARTIN and All

4. POPULATED PCB Power connectors Led power on Pull-Down Pull-up ALARM_H ALARM_T ALARM_P IT_30 IT_74 27/02/2024 - LPNHE - MARTIN and All

5. SIMULATION It is difficult to read anything about this simulation but the principle is as follows: in order to avoid an unwanted INTERLOCK, one of the ALARMS must be at 0 for at least 9 ms for it to be triggered. An ALARM is on going. INTERLOCK remains ON (ALARM too short) INTERLOCK goes down (ALARM too long) 27/02/2024 - LPNHE - MARTIN and All