Understanding Addressing Modes in 8086

Slide Note
Embed
Share

Delve into the world of addressing modes in the 8086 processor to comprehend how different types of operands are accessed and utilized during instruction execution. Explore immediate, direct, register, register-indirect, and other addressing modes with detailed examples.


Uploaded on Aug 08, 2024 | 1 Views


Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

E N D

Presentation Transcript


  1. Topic 6: Addressing Modes of 8086 By: Mr. Binu Joy

  2. Why study addressing modes? Addressing modes help us to understand the types of operands and the way they are accessed while executing an instruction.

  3. What are we going to study? Addressing modes We will see the types of addressing modes present in 8086. We will study each addressing mode with example.

  4. Types of addressing mode in 8086 Immediate addressing mode 1. Direct addressing mode 2. Register addressing mode 3. Register Indirect addressing mode 4. Indexed addressing mode 5. Register relative addressing mode 6. Base plus index addressing mode 7. Base relative plus index addressing mode 8.

  5. 1: Immediate addressing mode In this type of mode, immediate data is part of instruction and appears in the form of successive byte or bytes 10 ABH MOV AX,10ABH AX

  6. 2: Direct addressing mode In this type of addressing mode a 16-bit memory address is directly specified in the instruction as a part of it. Memory 22 33 22 33 5000 5001 MOV AX,[5000H] 5002 AX

  7. 3: Register addressing mode In this type of addressing mode, the data is stored in the register and it can be a 8-bit or 16-bit register. All the registers, except IP, may be used in this mode. 10 AB BH BL 10 AB BX MOV AL,BLH MOV AX,BXH AX FF 33 AH AL

  8. 4: Register Indirect addressing mode The address of the memory location which contains data or operand is determined in a indirect way, using the offset register. Memory 22 33 33 22 5000 AX 5001 MOV AX,[BX] 5002 BX 50 00

  9. Reflection Spot MOV [7000H],CX Q) Which addressing does instruction above belong, and why?

  10. Reflection Spot MOV [7000H],CX Q) Which addressing does instruction above belonging and why? Memory 22 33 Ans) Direct addressing mode 7000 7001 7002 CX 43 43 56 56

  11. 5: Indexed addressing mode In this addressing mode, offset of the operand is stored in one of the index registers. DS is the default segment for index register SI and DI. Memory 22 33 33 22 5000 AX 5001 MOV AX,[SI] 5002 SI 50 00

  12. 6: Register relative addressing mode In this mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment. Memory 44 33 33 44 5051 AX 5052 MOV AX, 50H[BX] 5053 + 50H = 5050H 50 00 Final Index Address Offset BX

  13. 7: Base plus index addressing mode In this mode the effective address is formed by adding content of a base register (any one of BX or BP) to the content of an index register (SI or DI). Default segment register DS. 12 34 34 12 3000 AX MOV AX, [BX] [SI] 3001 3002 + = 3000H 10 00 20 00 Final Index Address SI BX

  14. 8: Base relative plus index addressing mode In the effective address is formed by adding an 8 or 16-bit displacement with sum of contents of any one of the base registers (BX or BP) and any one of the index registers, in a default segment. 12 34 34 12 3050 AX MOV AX,50H[BX][SI] 3051 3052 = 3050H Final Index Address 50H + 10 00 20 00 SI BX

  15. Summery What we have learnt Different types of addressing modes present in 8086. Location of operands with respect to different addressing modes.

  16. References Advanced Microprocessors and Peripheral - By K Bhurchandi, A. K. Ray

  17. This presentation is licensed to the public Text is available under the Creative Commons Attribution-ShareAlike License

Related


More Related Content