Towards Single-Event Upset Detection in Hardware Secure RISC-V Processors
This research focuses on detecting single-event upsets (SEUs) in hardware-secure RISC-V processors in radiation environments, such as high-energy physics and space applications. Motivated by the potential data errors, unpredictable behavior, or crashes caused by SEUs, the study explores fault injection, simulation results, and the use of security features in the Ibex core to enhance SEU detection capabilities.
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Towards Single-Event Upset Detection in Hardware Secure RISC-V Processors Jeffrey Prinzie, Boris Engelen, Karel Appels, Levi Mari n, Na n Jonckers Electronic Circuits and Systems Advanced Integrated Sensing Lab (ADVISE)
Outline Motivation Research Methodology Fault Injection Simulation Results Conclusion TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 2 Processors
Motivation Processing systems in radiation environments High-Energy Physics Housekeeping processors (monitoring, configuration) Detector data processing (pixel/vertex/ML processors) Space applications Primary on-board computer Secondary computers (Data processing, accelerators, ) SEUs can cause data errors, unpredictable behavior or severe crashes TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 3 Processors
Motivation RISC-V RISC-V Instruction Set Architecture (ISA) Like ARM, x86, MIPS, SPARC, ... Available toolchain (compiler, ) Free to use - Open license Many open source cores/SoCs available Availability of source code for fault simulation (Minor) Modifications possible Not limited by vendor and export issues* (i.e. ARM) *More important for space applications TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 4 Processors
Motivation Ibex Core overview Open source 32-bit RISC-V CPU Written in SystemVerilog two-stage pipeline (third pipeline stage available) Different configurations available https://github.com/lowRISC/ibex TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 5 Processors
Alert outputs Dual core lockstep Bus integrity checking Register file write enable glitch detection and ECC Hardened PC Shadow CSRs Motivation Alert Minor Major Bus Security Features Ibex can implement a set of extra features to support security-critical applications Main strategy: Ibex core can detect external attacks due to corrupted states Alerts provided by dedicated signals Research Question: Can these built-in security features be used to detect SEUs within the Ibex core? https://ibex-core.readthedocs.io/en/latest/03_reference/security.html TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 6 Processors
Application program Research Methodology Makefile(s) Compile/Link bin Linker files Testbench architecture C/asm files Dhrystone/Coremark CoCoTB testbench Ibex RTL code Python models for SoC Data/Instruction memory Stdio Random SEU injection (Pre-pass with Genus to extract flip-flop list) Application code compiled and loaded in I-memory Xcelium RTL simulator Python testbench tb.py RTL (Ibex) I_memory.py D_memory.py SEU_inj.py TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 7 Processors
Research Methodology Run simulation Random time SEU inject Health checking Golden CRC Check CRC CPU state monitored each clock cycle CRC is accumulated on critical internal signals Checksum is signature for correct program flow: PC, D-addr, D-data, I-addr, RF, CSR y CRC error Check alert Abort sim Detected Undetected Golden simulation is performed initially n CRC is checked after SEU injection Continue simulaion Check alert False positive 300k SEUs injected TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 8 Processors
Fault Injection Simulation Results Results by symptom TB found CRC error but alert was low TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 9 Processors
Fault Injection Simulation Results Results by module Some errors are not detected! 10 2024
Fault Injection Simulation Results Improvement Observation: Some errors from register file are undetected But register file is protected with 39/32 Hsiao code = Simple? Simulations Run a few cases for undetected errors Trace internal alert signals Result: Alerts were raised internally but masked towards the output 11 2024
Fault Injection Simulation Results Improvement Modifications to the source code Opening issue on Github Bug? Modifications resulted in no undetected bit flips 12 2024
Fault Injection Simulation Results Area comparison Synthesis performed in 180nm ~2x area overhead Mostly due to lockstep datapath Overhead includes comparison logic TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 14 Processors
Conclusion Research Question: Can these built-in security features be used to detect SEUs within the Ibex core? Yes, but a slight modification to the core was necessary (bug?) Only error detection is present, how should we correct for errors? TMR directly corrects errors but large overhead Software/architecture correction required (checkpoint, rollback) Alert signals can be connected to CPU interrupt controller No scrubbing in register file Fault accumulate until Hsiao code cannot correct anymore Registers must be refreshed in software regularly (compiler add-on required) TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 15 Processors
Conclusion RISC-V provides opportunity for HEP and Space applications Hardware secure RISC-V cores can provide a solution to ride along a much larger community We can focus on SoC design Ibex RISC-V core was evaluated CoCoTB simulaton environment Most errors were detectable Small RTL correction was necessary to provide 100% coverage TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 16 Processors
Thank you Jeffrey Prinzie, Boris Engelen, Karel Appels, Levi Mari n, Na n Jonckers TWEPP 2023 - Towards Single-Event Upset Detetion in Hardware Secure RISC-V 17 Processors
