Introduction to Digital Logic Design - CSE 140 at UCSD

This content provides information about the Introduction to Digital Logic Design course (CSE 140) at the University of California, San Diego for the Spring 2017 semester. It includes details about the instructor, TAs, tutors, websites, textbooks, grading policy, logistics, and class materials. The course covers components and design techniques for digital systems and offers resources like online textbooks, zyBooks, and reference texts. It also highlights the significance of digital logic design in the context of Moore's Law and the Internet of Things.

• Digital Logic Design
• CSE 140
• UCSD
• Spring 2017
• Components

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1. Lecture 1: Introduction to Digital Logic Design CSE 140: Components and Design Techniques for Digital Systems Spring 2017 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1

2. Outlines Staff Instructor, TAs, Tutors Logistics Websites, Textbooks, Grading Policy Motivation Moore s Law, Internet of Things Scope Position among courses Coverage 2

3. Information about the Instructor Instructor: CK Cheng Education: Ph.D. in EECS UC Berkeley Industrial Experiences: Engineer of AMD, Mentor Graphics, Bellcore; Consultant for technology companies Email: ckcheng+140@ucsd.edu Office: Room 2130 CSE Building Office hours are posted on the course website 2-250PM Tu; 330-420PM Th Websites http://cseweb.ucsd.edu/~kuan http://cseweb.ucsd.edu/classes/sp17/cse140-a 3

4. Information about TAs and Tutors TAs He, Jennifer Lily email:p3he@ucsd.edu Jakate, Prateek Ravindra email:pjakate@ucsd.edu Knapp, Daniel Alan email:dknapp@ucsd.edu Luo, Mulong email:muluo@ucsd.edu (BSV CSE140L Winter 2017) Shih, Yishin email:y2shih@ucsd.edu (BSV CSE140L Winter 2017) Tutors Guan, Yuxiang email:yug049@ucsd.edu Huh, Sung Rim email:srhuh@ucsd.edu Li, Xuanang email:xul065@ucsd.edu Lu, Anthony email:anl176@ucsd.edu Park, Dong Won email:dwp003@ucsd.edu Wang, Moyang email:mowang@ucsd.edu Yao, Bohan email:boyao@ucsd.edu Yu, Yue email:yuy079@ucsd.edu Office hours will be posted on the course website 4

5. Logistics: Sites for the Class Class website http://cseweb.ucsd.edu/classes/sp17/cse140-a/index.html Index: Staff Contacts and Office Hrs Syllabus Grading policy Class notes Assignment: Homework and zyBook Activities Exercises: Solutions and Rubrics Forum (Piazza): Online Discussion *make sure you have access ACMS Labs ieng6: BSV mainly for CSE140L zyBook: UCSDCSE140ChengSpring2017 TritonEd: Score record 5

6. Logistics: Textbooks Required text: Online Textbook: Digital Design by F. Vahid 1. Sign up at zyBooks.com 2. Enter zyBook code UCSDCSE140ChengSpring2017 3. Fill email address with domain ucsd.edu 4. Fill section A01 or A02 5. Click Subscribe $48 BSV by Example, R.S. Nikhil and K. Czeck, 2010 (online). Reference texts (recommended and reserved in library) Digital Design, F. Vahid, 2010 (2nd Edition). Digital Design and Computer Architecture, D.M. Harris and S.L. Harris, Morgan Kaufmann, 2015 (ARM Edition). Digital Systems and Hardware/Firmware Algorithms, Milos D. Ercegovac and Tomas Lang. 6

7. Lecture: iCliker for Peer Instruction I will pose questions. You will Solo vote: Think for yourself and select answer Discuss: Analyze problem in teams of three Practice analyzing, talking about challenging concepts Reach consensus Class wide discussion: Led by YOU (students) tell us what you talked about in discussion that everyone should know. Many questions are open, i.e. no exact solutions. Emphasis is on reasoning and team discussion No solution will be posted 7

8. Logistics: Grading Grade on style, completeness and correctness zyBook exercises: 20% iClicker: 9% (by participation up to three quarters of classes) Homework: 15% (grade based on a subset of problems. If more than 85% of class fill out CAPE evaluations, the lowest homework score will be dropped) Midterm 1: 27% (T 5/2/17) Midterm 2: 28% (Th 6/8/17) Final: 1% (take home exam, due 10PM, Th 6/15/17) Grading: The best of the following The absolute: A- >90% ; B- >80% of total 100% score The curve: (A+,A,A-) top 33+ % of class; (B+,B,B-) second 33+ % The bottom: C- above 45% of absolute score. 8

9. A word on the grading components zyBook: Interactive learning experience Reset of answers causes no penalty No excuse for delay iClicker: Clarification of the concepts and team discussion Participation of three quarters of class No excuse for missing Homework: BSV (Bluespec System Verilog) will be used Practice for exams. Group discussion is encouraged However, we are required to write them individually for the best results Discount 10% loss of credit for each day after the deadline but no credit after the solution is posted. Metric: Posted solutions and rubrics, but not grading results 9

10. A word on the grading components Midterms: (Another) Indication of how well we have absorbed the material Samples will be posted for more practices. Solution and grading policy will be posted after the exam. Midterm 2 is not cumulative but requires a good command of the whole class. Final: Take home exam Application of the class materials Free to use libraries but no group discussion Fun and educational to work on. 10

11. BSV: Bluespec System Verilog High Level Language for Hardware (above Verilog) Promote modular design methodology Inventor: Arvind, MIT while he started an Ethernet router chip company. CSE140L Winter 2017 started BSV (Arvind, Gupta) CSE140L Spring 2017 adopts BSV (Isaac Chu) CSE140: Our homework will use BSV (learn by examples) 11

12. Course ProblemsCheating What is cheating? Studying together in groups is not cheating but encouraged Turned-in work must be completely your own. Copying someone else s solution on a HW or exam is cheating Both giver and receiver are equally culpable We have to address the issue once the cheating is reported by TAs or tutors. 12

13. Motivation Microelectronic technologies have revolutionized our world: cell phones, internet, rapid advances in medicine, etc. The semiconductor industry has grown from $21 billion in 1985 to $335 billion in 2015. 13

14. The Digital Revolution Integrated Circuit: Many digital operations on the same material Vacuum tubes Exponential Growth of Computation (1.6 x 11.1 mm) ENIAC Integrated Circuit Moore s Law Stored Program Model WWII 1949 1965 14

15. Building complex circuits Transistor 15

16. Robert Noyce, 1927 - 1990 Nicknamed Mayor of Silicon Valley Cofounded Fairchild Semiconductor in 1957 Cofounded Intel in 1968 Co-invented the integrated circuit 16

17. Gordon Moore Cofounded Intel in 1968 with Robert Noyce. Moore s Law: the number of transistors on a computer chip doubles every 1.5 years (observed in 1965) 17

18. Technology Trends: Moores Law Since 1975, transistor counts have doubled every two years. 18

19. Scope The purpose of this course is that we: Learn the principles of digital design Learn to systematically debug increasingly complex designs Design and build digital systems Learn what s under the hood of an electronic component 19

20. Position among CSE Courses Algos: CSE 100, 101 Application (ex: browser) CSE 120 CSE 131 CSE 140 Operating System (Mac OSX) Compiler Software Assembler Instruction Set Architecture Hardware CSE 140,141 Processor Memory I/O system Datapath & Control Digital Design Circuit Design Transistors Big idea: Coordination of many levels of abstraction Dan Garcia

21. Principle of Abstraction Application Software programs Operating Systems device drivers CSE 30 instructions registers Architecture focus of this course CSE 141 Micro- architecture datapaths controllers adders memories Logic CSE 140 Digital Circuits AND gates NOT gates Analog Circuits amplifiers filters Abstraction: Hiding details when they are not important transistors diodes Devices 21 Physics electrons

22. Scope: Overall Picture of CS140 Control Subsystem Data Path Subsystem Input Memory File Conditions Pointer Select Sequential machine Mux ALU Control Memory Register CLK: Synchronizing Clock Conditions 22 BSV: Design specification and modular design methodology

23. Combinational Logic vs Sequential Network x1 . . . xn x1 . . . xn xn x1 . . . fi(x,s) fi(x) fi(x) fi(x) fi(x) si CLK Sequential Networks 1. Memory 2. Time Steps (Clock) Combinational logic: yi = fi(x1,..,xn) yit = fi (x1t, ,xnt, s1t, ,smt) sit+1 = gi(x1t, ,xnt, s1t, ,smt) 23

24. Scope Subjects Building Blocks Theory Combinational Logic AND, OR, NOT, XOR Boolean Algebra Sequential Network AND, OR, NOT, FF Finite State Machine Standard Modules Operators, Interconnects, Memory Data Paths, Control Paths Arithmetics, Universal Logic System Design Methodologies 24

25. Combinational Logic Basics 25

26. What is a combinational circuit? No memory Realizes one or more functions Inputs and outputs can only have two discrete values Physical domain (usually, voltages) (Ground 0V, Vdd 1V) Mathematical domain : Boolean variables (True, False) Differentiate between different representations: physical circuit schematic diagram mathematical expressions 26

27. Boolean Algebra A branch of algebra in which the values of the variables belong to a set B (e.g. {0, 1}), has two operations {+, .} that satisfy the following four sets of laws. Commutative laws: a+b=b+a, a b=b a Distributive laws: a+(b c)=(a+b) (a+c), a (b+c)=a b+a c Identity laws: a+0=a, a 1=a Complement laws: a+a =1, a a =0 (x : the complement element of x) <27>

28. Representations of combinational circuits: The Schematic A Y B What is the simplest combinational circuit that you know? 28

29. Representations of combinational circuits Truth Table: Enumeration of all combinations Example: AND id 0 1 2 3 A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1 A Y=AB B 29

30. Boolean Algebra Similar to regular algebra but defined on sets with only three basic logic operations: Operator: . ,& Operator: + ,| Operator: ,! 1. Intersection: AND (2-input); 2. Union: OR (2-input); 3. Complement: NOT ( 1-input); &, |, ! Symbols in BSV <30>

31. Boolean algebra and switching functions One-input NOT (Complement, ) Two-input OR (+ ) Two-input AND ( ) AND OR A B Y A B Y NOT 0 0 0 0 1 1 1 0 1 1 1 1 A 1 A Y 0 0 0 0 1 0 1 0 0 1 1 1 A 1 0 1 1 0 A 1 A 0 A 0 0 A For an OR gate, 1 at input blocks the other inputs and dominates the output 0 at input passes signal A For an AND gate, 0 at input blocks the other inputs and dominates the output 1 at input passes signal A 31

32. Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+Y? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2 <32>

33. Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+X+Y? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2 <33>

34. Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+XY? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2 <34>

35. Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=(X+Y)Y? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2 <35>

36. So, what is the point of representing gates as symbols and Boolean expressions? Given the Boolean expression, we can draw the circuit it represents by cascading gates (and vice versa) ab a b ab + cd y=e (ab+cd) c d cd e Logic circuit vs. Boolean Algebra Expression 36

37. BSV Description: An example function Bit#(1) fy(Bit#(1) a, Bit#(1) b, Bit#(1) c, Bit#(1) d, Bit#(1) e); Bit#(1) y= e &((a &b) | (c&d)); return y; endfunction Bit#(n) type declaration says that a is n bit wide. ab a b ab + cd y=e (ab+cd) c d cd e 37

38. Next class Designing Combinational circuits 38