EFFECTIVE PREFETCHING
STREAM BUFFERS FOR
EFFECTIVE PREFETCHING
IN RISC-V
6.375 Final Project
Jonathan Terry
Introduction
•
What is a Stream Buffer?
•
Think of it as an aid to the cache, prefetching a
stream of data words in anticipation of certain
memory accesses.
•
At its core, it is a FIFO which deals with DDR3
preemptively so that the L1 cache miss penalty
is reduced!
Introduction
•
Upon a cache miss, the head of the stream
buffer is checked to see if it contains the
needed data.
•
If the data is not found, but is on its way via
the Stream Buffer, the cache waits for the
Stream Buffer’s response.
•
Otherwise, interact with DDR3 directly
Stream Buffer Architecture
Stream Buffer Architecture
System Architecture and Translating to BSV
Modifications to Cache and SB
•
Cache now supports checking a Stream
Buffer Controller (which may have a group
of Stream Buffers in it).
•
The Predictor system is also wrapped in
the Cache.
•
The Stream Buffer Controller contains all
machinery to manage SBs, make requests
to memory, and maintains the reallocation
policy.
The Request Scheduler
•
Absolutely needed in order to support
both Stream Buffer access and lower
memory access.
•
Without it, requests returned to
whatever rule fires first in whatever
module.
The Request Scheduler
Implementation Results
•
Generally positive results.
•
Was able to see a decent
improvement in processor
performance.
Performance on Assembly
Performance on Real Benchmarks
Average Performance vs. Stream Length
Overall Review
•
In all, I met almost all of my goals, the
biggest being improvement of
processor efficiency.
•
Was not able to make Markov
Predictor work.
•
Literature was not clear on specification.
•
Made the systems less modular and more
messy.
Future Design Explorations
•
Policies
•
Reallocation
•
Data Coherence
•
Research into Markov Model
Questions?
Thank You!
Think of a Stream Buffer as an aid to cache, prefetching data words preemptively to reduce L1 cache miss penalty. Upon a cache miss, the Stream Buffer is checked for needed data, enhancing system performance. Explore the architecture, system modifications, request scheduler, and implementation results for effective prefetching.
Download Presentation
Please find below an Image/Link to download the presentation.
The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.
E N D
Presentation Transcript
STREAM BUFFERS FOR EFFECTIVE PREFETCHING IN RISC-V 6.375 Final Project Jonathan Terry
Introduction What is a Stream Buffer? Think of it as an aid to the cache, prefetching a stream of data words in anticipation of certain memory accesses. At its core, it is a FIFO which deals with DDR3 preemptively so that the L1 cache miss penalty is reduced!
Introduction Upon a cache miss, the head of the stream buffer is checked to see if it contains the needed data. If the data is not found, but is on its way via the Stream Buffer, the cache waits for the Stream Buffer s response. Otherwise, interact with DDR3 directly
Modifications to Cache and SB Cache now supports checking a Stream Buffer Controller (which may have a group of Stream Buffers in it). The Predictor system is also wrapped in the Cache. The Stream Buffer Controller contains all machinery to manage SBs, make requests to memory, and maintains the reallocation policy.
The Request Scheduler Absolutely needed in order to support both Stream Buffer access and lower memory access. Without it, requests returned to whatever rule fires first in whatever module.
Implementation Results Generally positive results. Was able to see a decent improvement in processor performance.
Overall Review In all, I met almost all of my goals, the biggest being improvement of processor efficiency. Was not able to make Markov Predictor work. Literature was not clear on specification. Made the systems less modular and more messy.
Future Design Explorations Policies Reallocation Data Coherence Research into Markov Model
