DRAMs: Lightweight Memory Technology Overview

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Dynamic Random-Access Memories (DRAMs) are explored in depth, covering topics such as DRAM bit cells, operational characteristics, and logical diagrams. Learn about the destructive read nature, need for periodic refresh, and efficient hydraulic analogies for better understanding. Discover how DRAM read and write signaling work, including limitations and circuitry control involved in the process. Dive into the world of DRAM technology with this comprehensive guide.

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COMP541 Memories II: DRAMs Montek Singh Mar {27, 29}, 2019 1

Topics Previous lecture on memories: Read-Only Memories (ROMs) Static Random-Access Memory (SRAM) Today: Dynamic Random-Access Memory (DRAM) 2

Dynamic RAM (DRAM) Very lightweight bit-level memory a single capacitor holds charge (= value) no charge = 0 a single transistor acts as gate Write: connect switch & add charge to store a 1 then disconnect switch Read: read by connecting switch 3

DRAM Bit Cell Very lightweight contrast with SRAM DRAM cell consists of one transistor and one capacitor! SRAM cell has at least 6 transistors SRAM bit cell: DRAM bit cell: bitline bitline bitline wordline wordline 4

Hydraulic Analogy: Writing Storage Full (1) Empty (0) Pump fills tank to 1 value Pump drains tank to 0 value 5

Hydraulic Analogy: Reading Outside water begins at intermediate level (black wavy line) Tank had a 1 value raises water level Tank had a 0 value lowers water level 6

DRAM Characteristics Destructive Read When cell is read, charge is (partially) removed Must be restored after each read! Refresh Also, there s steady leakage and no transistor to constantly automatically replenish Charge must be restored periodically 7

DRAM Logical Diagram Control circuitry Core memory storage 8

DRAM Read Signaling Since DRAM is often on a separate chip number of pins available can be a limitation lower pin count by using same pins for row and column addresses Delay until data available 9

DRAM Write Signaling 10

DRAM Refresh Many strategies refresh circuits on chip here a simple row counter: reads and writes back Refresh circuitry 11

Refresh Timing Say, need to refresh every 64ms Distributed refresh Spread refresh out evenly over 64ms Say on a DRAM with 8192 rows (213), refresh window for each row = 64ms/8192=7.8 us Assume: time to refresh each row is 30ns Total time spent in refresh = 30ns * 8192 = 0.25ms but spread out Burst refresh Same 0.25ms, but all at once May not be good in a computer system an unlucky instruction will have to wait long Refresh takes low % of total time 0.25 ms / 64 ms = less than 4% 12

Bidirectional Lines Another optimization for reducing pins: Many chips have one set of data pins same pins used as data input for write operations same pins used as data output for read operations otherwise float them (i.e., tri-state) Makes sense because don t need both read/write data at once 13

Synchronous DRAM (SDRAM) Has a clock Common type in PCs late-90s Typical DRAMs still synchronous Multiple banks Pipelined Start read in one bank after another Come back and read the resulting values one after another 14

Modes of DRAM operation DRAMs optimized to read & write entire blocks or at least a few consecutive locations Several different modes normal/basic mode Nibble or Burst Mode Fast Page Mode Extended Data Out (EDO) Mode 15

Basic Mode of Operation Row Column Address RAS CAS Data Data Slowest mode Uses only single row and column address Row access is slow (60-70ns) compared to column access (5-10ns) Leads to three techniques for DRAM speed improvement Getting more bits out of DRAM on one access given timing constraints Pipelining the various operations to minimize total time Segmenting the data in such a way that some operations are eliminated for a given set of accesses 16

Nibble (or Burst) Mode RAS RA ---- ---- CAS CA ---- ---- CAS ---- ---- CAS ---- ---- CAS ---- D1 D2 D3 D4 Several consecutive columns are accessed Only first column address is explicitly specified Rest are internally generated using a counter 17

Fast Page Mode RAS RA ---- ---- CAS CA1 ---- D1 ---- CAS CA2 ---- D2 ---- CAS CA3 ---- D3 ---- CAS CA4 ---- D4 Accesses arbitrary columns within same row Static column mode is similar 18

EDO Mode RAS RA ---- ---- CAS CA1 ---- CAS CA2 D1 ---- CAS CA3 D2 ---- CAS CA4 D3 ---- CAS CA5 D4 ---- CAS CA6 D5 ---- CAS CA7 D6 ---- Arbitrary column addresses Pipelined EDO = Extended Data Out Has other modes like burst EDO , which allows reading of a fixed number of bytes starting with each specified column address 19

DDR DRAM Double Data Rate (DDR) SDRAM Transfers data on both edges of the clock Currently popular You get two memory accesses per clock cycle! 20

RAMBUS DRAM (RDRAM) Another attempt to alleviate pin limits Many (16-32) banks per chip Made to be read/written in packets Up to 1200MHz bus speeds XDR 8 bits per clock, 16-bit wide bus, 6.4GB But DDR doing very well also Quite expensive almost disappeared from consumer PCs still present in servers and specialized chips 21

DRAM Controllers Very common to have a separate chip/module that controls memory Handles banks Handles refresh Multiplexes column and row addresses RAS and CAS timing Called Northbridge on PC chip set 22

Conclusions RAMs with different characteristics For different purposes Static RAM Simple to use, small, expensive Fast, used for cache Dynamic RAM Complex to interface, largest, cheap Needs periodic refresh 23