Assembly Programming in CSE351 Spring 2017
Assembly Programming I
CSE 351 Spring 2017
Instructor:
Ruth Anderson
Teaching Assistants:
Dylan Johnson
Kevin Bi
Linxing Preston Jiang
Cody Ohlsen
Yufang Sun
Joshua Curtis
Administrivia
Lab 1 due Friday (4/14)
Prelim submission (3+ of
bits.c
) due on TONIGHT (4/10).
Turn in whatever you have at that time (drop box closes at
11:59pm), no lates. Worth a small part (no more than 10%)
of total points for lab 1.
Homework 2 due next Wednesday (4/19)
2
Roadmap
3
car *
c = malloc(sizeof(
car
));
c->miles = 100;
c->gals = 17;
float
mpg = get_mpg(c);
free(c);
Car c = new Car();
c.setMiles(100);
c.setGals(17);
float mpg =
c.getMPG();
get_mpg:
pushq
%rbp
movq
%rsp, %rbp
...
popq
%rbp
ret
Java:
C:
Assembly
language:
Machine
code:
0111010000011000
100011010000010000000010
1000100111000010
110000011111101000011111
Computer
system:
OS:
Memory & data
Integers & floats
x86 assembly
Procedures & stacks
Executables
Arrays & structs
Memory & caches
Processes
Virtual memory
Memory allocation
Java vs. C
Translation
4
What makes programs run fast(er)?
Hardware
User
program
in C
Assembler
C
compiler
Code Time
Compile Time
Run Time
.exe
file
.c
file
C Language
HW Interface Affects Performance
5
x86-64
Intel Pentium
4
Intel Core 2
Intel
Core i7
AMD Opteron
AMD Athlon
GCC
ARMv8
(AArch64/A64)
ARM Cortex-A53
Apple A7
Clang
Your
program
Program
B
Program
A
Compiler
Source code
Architecture
Different applications
or algorithms
Perform optimizations,
generate instructions
Different
implementations
Hardware
Instruction set
Instruction Set Architectures
The ISA defines:
The system’s state (
e.g.
registers, memory, program
counter)
The instructions the CPU can execute
The effect that each of these instructions will have on the
system state
6
Instruction Set Philosophies
Complex Instruction Set Computing
(CISC):
Add more
and more elaborate and specialized instructions as
needed
Lots of tools for programmers to use, but hardware must be
able to handle all instructions
x86-64 is CISC, but o
nly a small subset of instructions
encountered with Linux programs
Reduced Instruction Set Computing
(RISC):
Keep
instruction set small and regular
Easier to build fast hardware
Let software do the complicated operations by composing
simpler ones
7
General ISA Design Decisions
Instructions
What instructions are available? What do they do?
How are they encoded?
Registers
How many registers are there?
How wide are they?
Memory
How do you specify a memory location?
8
General ISA Design Decisions
Instructions
What instructions are available? What do they do?
How are they encoded?
Instructions are data!
Registers
How many registers are there?
How wide are they?
Size of a word
Memory
How do you specify a memory location?
Different ways to
build up an address
9
Mainstream ISAs
Macbooks & PCs
(Core i3, i5, i7, M)
x86-64 Instruction Set
Smartphone-like devices
(iPhone, iPad, Raspberry Pi)
ARM Instruction Set
Digital home & networking
equipment
(Blu-ray, PlayStation 2)
MIPS Instruction Set
10
Definitions
Architecture (ISA):
The parts of a processor design
that one needs to understand to write assembly code
“What is directly visible to software”
Microarchitecture:
Implementation of the
architecture
CSE/EE 469, 470
Are the following part of the architecture?
Number of registers?
How about CPU frequency?
Cache size? Memory size?
11
Definitions
Architecture (ISA):
The parts of a processor design
that one needs to understand to write assembly code
“What is directly visible to software”
Microarchitecture:
Implementation of the
architecture
CSE/EE 469, 470
Are the following part of the architecture?
Number of registers?
Yes
How about CPU frequency?
No
Cache size? Memory size?
No
12
CPU
Assembly Programmer’s View
Programmer-visible state
PC: the Program Counter (
%rip
in x86-64)
•
Address of next instruction
Named registers
•
Together in “register file”
•
Heavily used program data
Condition codes
•
Store status information about most recent
arithmetic operation
•
Used for conditional branching
13
PC
Registers
Memory
•
Code
•
Data
•
Stack
Addresses
Data
Instructions
Condition
Codes
Memory
Byte-addressable array
Code and user data
Includes
the Stack
(for
supporting procedures)
x86-64 Assembly “Data Types”
Integral data of 1, 2, 4, or 8 bytes
Data values
Addresses (untyped pointers)
Floating point data of 4, 8, 10 or 2x8 or 4x4 or 8x2
Different registers for those (
e.g.
%xmm1
,
%ymm2
)
Come from
extensions to x86
(SSE, AVX,
…
)
No aggregate types such as arrays or structures
Just contiguously allocated bytes in memory
Two common syntaxes
“AT&T”: used by our course, slides, textbook, gnu tools, …
“Intel”: used by Intel documentation, Intel tools, …
Must know which you’re reading
14
What is a Register?
A location in the CPU that stores a small amount of
data, which can be accessed very quickly
(once every
clock cycle)
Registers have
names
, not
addresses
In assembly, they start with
%
(
e.g.
%rsi
)
Registers are at the heart of assembly programming
They are a precious commodity in all architectures, but
especially
x86
15
x86-64 Integer Registers – 64 bits wide
Can reference low-order 4 bytes (also low-order 2 & 1 bytes)
16
Some History: IA32 Registers – 32 bits wide
17
Name Origin
(mostly obsolete)
Memory
vs.
Registers
Addresses
vs.
Names
0x7FFFD024C3DC
%rdi
Big
vs.
Small
~ 8 GiB
(16 x 8 B) =
128
B
Slow
vs.
Fast
~50-100 ns
sub-nanosecond timescale
Dynamic
vs.
Static
Can “grow” as needed
fixed number in hardware
while program runs
18
Three Basic Kinds of Instructions
1)
Transfer data between memory and register
Load
data from memory into register
•
%reg
= Mem[address]
Store
register data into memory
•
Mem[address] =
%reg
2)
Perform arithmetic operation on register or memory
data
c = a + b; z = x << y; i = h & g;
3)
Control flow: what instruction to execute next
Unconditional jumps to/from procedures
Conditional branches
19
Remember:
Memory
is indexed just like an
array of bytes!
Operand types
Immediate:
Constant integer data
Examples:
$0x400
,
$-533
Like C literal, but prefixed with
‘$’
Encoded with 1, 2, 4, or 8 bytes
depending on the instruction
Register:
1 of 16 integer registers
Examples:
%rax
,
%r13
But
%rsp
reserved for special use
Others have special uses for particular
instructions
Memory:
Consecutive bytes of memory
at a computed address
Simplest example:
(%rax)
Various other “address modes”
20
Moving Data
General form:
mov_ source, destination
Missing letter (
_
) specifies size of operands
Note that due to backwards-compatible support for 8086
programs (16-bit machines!), “word” means 16 bits = 2 bytes
in x86 instruction names
Lots of these in typical code
movb src, dst
Move 1-byte “
b
yte”
movw src, dst
Move 2-byte “
w
ord”
21
movl src, dst
Move 4-byte “
l
ong word”
movq src, dst
Move 8-byte “
q
uad word”
movq
Operand Combinations
22
Cannot do memory-memory transfer with a single
instruction
How would you do it?
var_a = 0x4;
*p_a = -147;
var_d = var_a;
*p_d = var_a;
var_d = *p_a;
Question
Which of the following statements is TRUE?
A.
For
float f
, (
f+2 == f+1+1)
always
returns TRUE
B.
The width of a “word” is part of a system’s
architecture
(as opposed to
microarchitecture
)
C.
Having more registers increases the performance
of the hardware, but decreases the performance
of the software
D.
Mem to Mem (src to dst) is the only disallowed
operand combination in x86-64
23
Summary
Converting between integral and floating point data
types
does
change the bits
Floating point rounding is a HUGE issue!
•
Limited mantissa bits cause inaccurate representations
•
Floating point arithmetic is NOT associative or distributive
x86-64 is a complex instruction set computing (CISC)
architecture
Registers
are named locations in the CPU for holding
and manipulating data
x86-64 uses 16 64-bit wide registers
Assembly operands include immediates, registers,
and data at specified memory locations
24
Explore the world of assembly programming through CSE351 in Spring 2017. Delve into topics like memory, data, x86 assembly, procedures, executables, arrays, and more. Learn about the differences in Java and C, machine code, hardware, compilers, and the factors that influence program performance. Understand instruction set architectures and their impact on system state, CPU operations, memory, and registers.
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Presentation Transcript
L07: Assembly Programming I CSE351, Spring 2017 Assembly Programming I CSE 351 Spring 2017 Instructor: Ruth Anderson Teaching Assistants: Dylan Johnson Kevin Bi Linxing Preston Jiang Cody Ohlsen Yufang Sun Joshua Curtis
L07: Assembly Programming I CSE351, Spring 2017 Administrivia Lab 1 due Friday (4/14) Prelim submission (3+ of bits.c) due on TONIGHT (4/10). Turn in whatever you have at that time (drop box closes at 11:59pm), no lates. Worth a small part (no more than 10%) of total points for lab 1. Homework 2 due next Wednesday (4/19) 2
L07: Assembly Programming I CSE351, Spring 2017 Roadmap Memory & data Integers & floats x86 assembly Procedures & stacks Executables Arrays & structs Memory & caches Processes Virtual memory Memory allocation Java vs. C C: Java: Car c = new Car(); c.setMiles(100); c.setGals(17); float mpg = c.getMPG(); car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c); Assembly language: get_mpg: pushq %rbp movq %rsp, %rbp ... popq %rbp ret OS: Machine code: 0111010000011000 100011010000010000000010 1000100111000010 110000011111101000011111 Computer system: 3
L07: Assembly Programming I CSE351, Spring 2017 Translation Code Time Compile Time Run Time User program in C C Assembler Hardware compiler .c file .exe file What makes programs run fast(er)? 4
L07: Assembly Programming I CSE351, Spring 2017 HW Interface Affects Performance Hardware Architecture Instruction set Source code Different applications or algorithms Compiler Perform optimizations, generate instructions Different implementations Intel Pentium 4 C Language Intel Core 2 Program A x86-64 Intel Core i7 GCC AMD Opteron Program B AMD Athlon Clang Your program ARMv8 (AArch64/A64) ARM Cortex-A53 Apple A7 5
L07: Assembly Programming I CSE351, Spring 2017 Instruction Set Architectures The ISA defines: The system s state (e.g. registers, memory, program counter) The instructions the CPU can execute The effect that each of these instructions will have on the system state CPU PC Memory Registers 6
L07: Assembly Programming I CSE351, Spring 2017 Instruction Set Philosophies Complex Instruction Set Computing (CISC): Add more and more elaborate and specialized instructions as needed Lots of tools for programmers to use, but hardware must be able to handle all instructions x86-64 is CISC, but only a small subset of instructions encountered with Linux programs Reduced Instruction Set Computing (RISC): Keep instruction set small and regular Easier to build fast hardware Let software do the complicated operations by composing simpler ones 7
L07: Assembly Programming I CSE351, Spring 2017 General ISA Design Decisions Instructions What instructions are available? What do they do? How are they encoded? Registers How many registers are there? How wide are they? Memory How do you specify a memory location? 8
L07: Assembly Programming I CSE351, Spring 2017 General ISA Design Decisions Instructions What instructions are available? What do they do? How are they encoded? Instructions are data! Registers How many registers are there? How wide are they? Size of a word Memory How do you specify a memory location? Different ways to build up an address 9
L07: Assembly Programming I CSE351, Spring 2017 Mainstream ISAs Macbooks & PCs (Core i3, i5, i7, M) x86-64 Instruction Set Smartphone-like devices (iPhone, iPad, Raspberry Pi) ARM Instruction Set Digital home & networking equipment (Blu-ray, PlayStation 2) MIPS Instruction Set 10
L07: Assembly Programming I CSE351, Spring 2017 Definitions Architecture (ISA): The parts of a processor design that one needs to understand to write assembly code What is directly visible to software Microarchitecture: Implementation of the architecture CSE/EE 469, 470 Are the following part of the architecture? Number of registers? How about CPU frequency? Cache size? Memory size? 11
L07: Assembly Programming I CSE351, Spring 2017 Definitions Architecture (ISA): The parts of a processor design that one needs to understand to write assembly code What is directly visible to software Microarchitecture: Implementation of the architecture CSE/EE 469, 470 Are the following part of the architecture? Number of registers? Yes How about CPU frequency? No Cache size? Memory size? No 12
L07: Assembly Programming I CSE351, Spring 2017 Assembly Programmer s View CPU Memory Addresses Registers Code Data Stack PC Data Condition Codes Instructions Programmer-visible state PC: the Program Counter (%rip in x86-64) Address of next instruction Named registers Memory Byte-addressable array Code and user data Includes the Stack (for supporting procedures) Together in register file Heavily used program data Condition codes Store status information about most recent arithmetic operation Used for conditional branching 13
L07: Assembly Programming I CSE351, Spring 2017 x86-64 Assembly Data Types Integral data of 1, 2, 4, or 8 bytes Data values Addresses (untyped pointers) Floating point data of 4, 8, 10 or 2x8 or 4x4 or 8x2 Different registers for those (e.g.%xmm1, %ymm2) Come from extensions to x86 (SSE, AVX, ) Not covered In CSE 351 No aggregate types such as arrays or structures Just contiguously allocated bytes in memory Two common syntaxes AT&T : used by our course, slides, textbook, gnu tools, Intel : used by Intel documentation, Intel tools, Must know which you re reading 14
L07: Assembly Programming I CSE351, Spring 2017 What is a Register? A location in the CPU that stores a small amount of data, which can be accessed very quickly (once every clock cycle) Registers have names, not addresses In assembly, they start with % (e.g.%rsi) Registers are at the heart of assembly programming They are a precious commodity in all architectures, but especially x86 15
L07: Assembly Programming I CSE351, Spring 2017 x86-64 Integer Registers 64 bits wide %rax %rbx %rcx %rdx %rsi %rdi %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 %eax %r8d %ebx %r9d %ecx %r10d %edx %r11d %esi %r12d %edi %r13d %rsp %rbp %esp %r14d %ebp %r15d Can reference low-order 4 bytes (also low-order 2 & 1 bytes) 16
L07: Assembly Programming I CSE351, Spring 2017 Some History: IA32 Registers 32 bits wide %eax %ax %ah %al accumulate %ecx %cx %ch %cl counter general purpose %edx %dx %dh %dl data %ebx %bx %bh %bl base %esi %si source index %edi %di destination index %esp %sp stack pointer %ebp %bp base pointer 16-bit virtual registers (backwards compatibility) Name Origin (mostly obsolete) 17
L07: Assembly Programming I CSE351, Spring 2017 Memory vs. Registers Addresses 0x7FFFD024C3DC vs. Names %rdi Big ~ 8 GiB vs. Small (16 x 8 B) = 128 B Slow ~50-100 ns vs. Fast sub-nanosecond timescale Dynamic Can grow as needed while program runs vs. Static fixed number in hardware 18
L07: Assembly Programming I CSE351, Spring 2017 Three Basic Kinds of Instructions 1)Transfer data between memory and register Load data from memory into register %reg = Mem[address] Store register data into memory Mem[address] = %reg Remember: Memory is indexed just like an array of bytes! 2)Perform arithmetic operation on register or memory data c = a + b; z = x << y; i = h & g; 3)Control flow: what instruction to execute next Unconditional jumps to/from procedures Conditional branches 19
L07: Assembly Programming I CSE351, Spring 2017 Operand types %rax %rcx %rdx %rbx %rsi %rdi %rsp %rbp Immediate: Constant integer data Examples: $0x400, $-533 Like C literal, but prefixed with $ Encoded with 1, 2, 4, or 8 bytes depending on the instruction Register: 1 of 16 integer registers Examples: %rax, %r13 But %rsp reserved for special use Others have special uses for particular instructions Memory: Consecutive bytes of memory at a computed address Simplest example: (%rax) Various other address modes %rN 20
L07: Assembly Programming I CSE351, Spring 2017 Moving Data General form: mov_ source, destination Missing letter (_) specifies size of operands Note that due to backwards-compatible support for 8086 programs (16-bit machines!), word means 16 bits = 2 bytes in x86 instruction names Lots of these in typical code movb src, dst Move 1-byte byte movl src, dst Move 4-byte long word movw src, dst Move 2-byte word movq src, dst Move 8-byte quad word 21
L07: Assembly Programming I CSE351, Spring 2017 movq Operand Combinations Source Dest Src, Dest C Analog movq $0x4, %rax var_a = 0x4; Reg Imm movq $-147, (%rax) *p_a = -147; Mem movq movq %rax, %rdx var_d = var_a; Reg Reg movq %rax, (%rdx) *p_d = var_a; Mem movq (%rax), %rdx var_d = *p_a; Mem Reg Cannot do memory-memory transfer with a single instruction How would you do it? 22
L07: Assembly Programming I CSE351, Spring 2017 Question Which of the following statements is TRUE? A. For float f, (f+2 == f+1+1) always returns TRUE B. The width of a word is part of a system s architecture (as opposed to microarchitecture) C. Having more registers increases the performance of the hardware, but decreases the performance of the software D. Mem to Mem (src to dst) is the only disallowed operand combination in x86-64 23
L07: Assembly Programming I CSE351, Spring 2017 Summary Converting between integral and floating point data types does change the bits Floating point rounding is a HUGE issue! Limited mantissa bits cause inaccurate representations Floating point arithmetic is NOT associative or distributive x86-64 is a complex instruction set computing (CISC) architecture Registers are named locations in the CPU for holding and manipulating data x86-64 uses 16 64-bit wide registers Assembly operands include immediates, registers, and data at specified memory locations 24
