TI Information Selective Disclosure in Electronic Layout Review
Review of selective disclosure recommendations for TPS546D24A layout design by TI, including tips for noise reduction, component placement, and signal routing to optimize performance and reduce interference. Detailed images and guidelines for improving layout quality and signal integrity are provided.
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TPS546D24A Layout Review SR-MVB Joseph Conrad 12/27/23 1 TI Information Selective Disclosure
VOSNS/GOSNS Route further away from the power inductor to avoid noise coupling. Remove the 10Ohm resistor to local output cap bank. 2 TI Information Selective Disclosure
SW node Shrink the SW node on both devices. This will help radiate less noise to sensitive traces. Move the inductor closer to the IC if design rules allow 3 TI Information Selective Disclosure
Pin strapping pins (MSEL1,MSEL2, ADRSEL, VSEL, For high side resistor divider resistors: reduce trace parasitic by removing the transition from SIG7 to SIG3. Just have one transition from BOT to SIG3 to TOP 4 TI Information Selective Disclosure
SYNC Try to avoid having SYNC line near sensitive analog traces/pins like VSHARE 5 TI Information Selective Disclosure
Input/Output Caps Ensure there are vias at input cap pads to stitch top and bottom layers together. The ones nearest the IC especially are important for proper decoupling Output caps should also have vias at every capacitor pad, similar to what is drawn to the right 6 TI Information Selective Disclosure
