Enhancing Data Reception Performance with GPU Acceleration in CCSDS 131.2-B Protocol

Explore the utilization of Graphics Processing Unit (GPU) accelerators for high-performance data reception in a Software Defined Radio (SDR) system following the CCSDS 131.2-B protocol. The research, presented at the EDHPC 2023 Conference, focuses on implementing a state-of-the-art GP-GPU receiver to improve performance in processing telemetry data under variable channel conditions, particularly beneficial for Earth observation missions with a significant data load.

Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

• Data reception
• GPU acceleration
• CCSDS 131.2-B
• Software Defined Radio
• High performance

kellan Follow

Uploaded on Mar 20, 2024 | 0 Views

Presentation Transcript

1. EDHPC 2023 European Data Handling & Data Processing Conference for Space A Software Defined Radio for CCSDS 131.2-B protocol: exploiting Graphics Processing Unit accelerator for high performance data reception Roberto Ciardi, Gianluca Giuffrida, Matteo Bertolucci, Luca Fanucci

2. Roberto Ciardi PhD Student @ University of Pisa Department of Information Engineering Industrial PhD Embedded Software Engineer @ IngeniArs S.r.l. EDHPC 2023 Roberto Ciardi University of Pisa 2

3. Outline Introduction: CCSDS 131.2-B standard CCSDS Receiver Software Defined Radio CCSDS 131.2-B SDR Receiver: State of The Art GP-GPU Receiver implementation Performance Conclusion EDHPC 2023 Roberto Ciardi University of Pisa 3

4. Outline Introduction: CCSDS 131.2-B standard CCSDS Receiver Software Defined Radio CCSDS 131.2-B SDR Receiver: State of The Art GP-GPU Receiver implementation Performance Conclusion EDHPC 2023 Roberto Ciardi University of Pisa 4

5. CCSDS 131.2-B Standard Coding and Modulation for telemetry Maximize average data transfer under variable channel conditions Noisy Channel 27 ModCods (ACM) Large quantity of data Earth Observation missions Complex and expensive HW for transmitters/receivers EDHPC 2023 Roberto Ciardi University of Pisa 5

6. CCSDS 131.2-B Receiver Recover amplitude, timing, frequency and phase Decode signal Turbo-decoder Recover ACM Demodulation and Decoding From Codeword to bits 500 MBaud (~60k codewords per second) Absence of high performance SW solutions EDHPC 2023 Roberto Ciardi University of Pisa 6

7. Outline Introduction: CCSDS 131.2-B standard CCSDS Receiver Software Defined Radio CCSDS 131.2-B SDR Receiver: State of The Art GP-GPU Receiver implementation Performance Conclusion EDHPC 2023 Roberto Ciardi University of Pisa 7

8. Software Defined Radio Radio communication system Replace HW components (e.g., FPGA, ASIC) with SW components Filters, Modulators/Demodulators, Decoders etc. Flexibility Extensibility Cheaper maintenance Upgradable FPGA ASIC High ad-hoc embedded sys Performance Processors GPUs EDHPC 2023 Roberto Ciardi University of Pisa 8

9. Outline Introduction: CCSDS 131.2-B standard CCSDS Receiver Software Defined Radio CCSDS 131.2-B SDR Receiver: State of The Art GP-GPU Receiver implementation Performance Conclusion EDHPC 2023 Roberto Ciardi University of Pisa 9

10. SW State of The Art Electrical Ground Support Equipment (EGSE) SDR for testing CCSDS 131.2-B compliant transmitters Emulates entire communication chain Serial processing Intel Core i7-7700K CPU Very slow (3 s per 1 codeword) L. Diana, G. Giuffrida, M. Marini, R. Cassettari, D. Davalle, and L. Fanucci, Sccc sw egse: A software simulator of a satellite downlink communication compliant with the ccsds 131.2-b-1 standard, with hardware-in-the-loop capabilities, in 2019 8th International Workshop on Tracking, Telemetry and Command Systems for Space Applications (TTC). IEEE, 2019, pp. 1 6 EDHPC 2023 Roberto Ciardi University of Pisa 10

11. Outline Introduction: CCSDS 131.2-B standard CCSDS Receiver Software Defined Radio CCSDS 131.2-B SDR Receiver: State of The Art GP-GPU Receiver implementation Performance Conclusion EDHPC 2023 Roberto Ciardi University of Pisa 11

12. Rationale for SDR Receiver Exploit commercial GPU Flexible Easy to deploy Tunable Low Cost Solution Low performance Can replace HW solutions for specific science missions EDHPC 2023 Roberto Ciardi University of Pisa 12

13. General Purpose Graphic Processing Unit CPU Few Cores Serial computation Different Tasks Different Threads Maximize Instruction Throughput GPU Thousands of Cores Parallel computation Same Task Maximize Data Throughput Single Instruction Multiple Data (SIMD) EDHPC 2023 Roberto Ciardi University of Pisa 13

14. CCSDS 131.2-B Receiver Structure Encoded Signal Frequency Recovery Phase Recovery Time Recovery Constellation Demapper SCCC Decoder Decoded Bits EDHPC 2023 Roberto Ciardi University of Pisa 14

15. SCCC Decoder Serial Concatenated Convolutional Codes (SCCC) Perform iterative symbols decoding and interleaving SCCC Decoder Input: Codeword More than 65k samples (ACM 27) Use of complex soft-in-soft-out (SISO) decoders Output: Decoded Bits Encoded Codeword SCCC Decoder Decoded Bits EDHPC 2023 Roberto Ciardi University of Pisa 15

16. SCCC Decoder Structure De- SISO2 Decoder De- SISO1 Decoder De- Input Codeword Output Bits Puncturing Interleaver Puncturing - - Puncturing Interleaver EDHPC 2023 Roberto Ciardi University of Pisa 16

17. Parallelization Serial Computation Module EDHPC 2023 Roberto Ciardi University of Pisa 17

18. Parallelization Serial Parallel Computation Computation Module Module EDHPC 2023 Roberto Ciardi University of Pisa 18

19. CCSDS 131.2-B SDR Receiver Commercial GPU NVIDIA Quadro Rtx 4000 CUDA framework Parallelization of each module Modular code Factory Method Design Pattern Both CPU and GPU code Tuning of each part of the Receiver DE PUN SISO 2 DE IL SISO 1 DE PUN Input Output - PUN IL - EDHPC 2023 Roberto Ciardi University of Pisa 19

20. Outline Introduction: CCSDS 131.2-B standard CCSDS Receiver Software Defined Radio CCSDS 131.2-B SDR Receiver: State of The Art GP-GPU Receiver implementation Performance Conclusion EDHPC 2023 Roberto Ciardi University of Pisa 20

21. Test Case Transmitter SW implementation Channel Emulation Additive White Gaussian Noise Doppler Phase Noise Evaluation of Rx speed performance Evaluation of Rx error correction (BER curves) SW Transmitter Channel Impairments SDR Receiver EDHPC 2023 Roberto Ciardi University of Pisa 21

22. Benchmark SW EGSE Matlab Version GPU implementation Higher performance than SW EGSE and other SW implementation Implementation Time for a CWs (ms) ACM 1 ACM 15 ACM 27 SW EGSE ~3000 ~13000 ~25000 Matlab Script 876,15 2182,23 4519,16 GP-GPU SDR 1,32 2,88 4,24 EDHPC 2023 Roberto Ciardi University of Pisa 22

23. Greenbook BER Curves ACM 1-12 EDHPC 2023 Roberto Ciardi University of Pisa 23

24. BER Curves ACM 1-12 EDHPC 2023 Roberto Ciardi University of Pisa 24

25. BER Curves ACM 1-12 EDHPC 2023 Roberto Ciardi University of Pisa 25

26. Greenbook BER Curves ACM 13-27 EDHPC 2023 Roberto Ciardi University of Pisa 26

27. BER Curves ACM 13-27 EDHPC 2023 Roberto Ciardi University of Pisa 27

28. BER Curves ACM 13-27 EDHPC 2023 Roberto Ciardi University of Pisa 28

29. Outline Introduction: CCSDS 131.2-B standard CCSDS Receiver Software Defined Radio CCSDS 131.2-B SDR Receiver: State of The Art GP-GPU Receiver implementation Performance Conclusion EDHPC 2023 Roberto Ciardi University of Pisa 29

30. Preliminary Results BER curves Similar slope w.r.t. ideal curves 0.3/0.6 shift on Eb/N0 Speed performance: Up to 10 MBaud for ACM 1 Up to 4 MBaud for ACM 27 Current HW can reach 500 MBaud Suitable for science missions EDHPC 2023 Roberto Ciardi University of Pisa 30

31. Conclusion Innovative Software-Defined Radio (SDR) receiver Low Cost Easy to deploy Alternative to complex and expensive State-Of-The-Art HW receivers Future work: Higher performance GPUs Use more GPUs in parallel EDHPC 2023 Roberto Ciardi University of Pisa 31

32. Thank You COME VISIT OUR BOOTH #1 CONTACTS: roberto.ciardi@phd.unipi.it roberto.ciardi@ingeniars.com EDHPC 2023 Roberto Ciardi University of Pisa 32

33. References [1] CCSDS 131.2-B-1 Recommended Standard, Flexible Advanced Coding and Modulation Scheme for High Rate Telemetry Applications, 2012. [2] M. Bertolucci, F. Falaschi, R. Cassettari, D. Davalle, and L. Fanucci, A comprehensive trade-off analysis on the ccsds 131.2-b-1 extended modcod (sccc-x) implementation, in 2020 23rd Euromicro Conference on Digital System Design (DSD). IEEE, 2020, pp. 126 132. [3] M. Bertolucci, R. Cassettari, and L. Fanucci, On the frequency carrier offset and symbol timing estimation for ccsds 131.2-b-1 high data-rate telemetry receivers, Sensors, vol. 21, no. 9, p. 2915, 2021. [4] L. Diana, G. Giuffrida, M. Marini, R. Cassettari, D. Davalle, and L. Fanucci, Sccc sw egse: A software simulator of a satellite downlink communication compliant with the ccsds 131.2-b-1 standard, with hardware-in-the-loop capabilities, in 2019 8th International Workshop on Tracking, Telemetry and Command Systems for Space Applications (TTC). IEEE, 2019, pp. 1 6. [5] M. N. Sadiku and C. M. Akujuobi, Software-defined radio: a brief overview, Ieee Potentials, vol. 23, no. 4, pp. 14 15, 2004. [6] T. Ulversoy, Software defined radio: Challenges and opportunities, IEEE Communications Surveys & Tutorials, vol. 12, no. 4, pp. 531 550, 2010. [7] T. J. Kacpura, W. M. Eddy, C. R. Smith, and J. Liebetreu, Software defined radio architecture contributions to next generation space communications, in 2015 IEEE Aerospace Conference. IEEE, 2015, pp. 1 12. [8] M. Pugh, I. Kuperman, F. Aguirre, H. Mojaradi, C. Spurgers, M. Kobayashi, E. Satorius, and T. Jedrey, The universal space transponder: A next generation software defined radio, in 2017 IEEE Aerospace Conference. IEEE, 2017, pp. 1 14. [9] M. Ujaldon, High performance computing and simulations on the gpu using cuda, in 2012 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2012, pp. 1 7. [10] D. Kirk et al., Nvidia cuda software and gpu parallel computing architecture, in ISMM, vol. 7, 2007, pp. 103 104. [11] B. Daga, A. Bhute, and A. Ghatol, Implementation of parallel image processing using nvidia gpu framework, in Advances in Computing, Communication and Control: International Conference, ICAC3 2011, Mumbai, India, January 28-29, 2011. Proceedings. Springer, 2011, pp. 457 464. [12] S. van der Heide, R. S. Luis, B. J. Puttnam, G. Rademacher, T. Koonen, S. Shinada, Y. Awaji, H. Furukawa, and C. Okonkwo, 10,000 km straight-line transmission using a real-time software-defined gpu- based receiver, in 2021 Optical Fiber Communications Conference and Exhibition (OFC), 2021, pp. 1 3. [13] R. Ciardi, G. Giuffrida, M. Bertolucci, E. Pagani, and L. Fanucci, Ccsds 131.2-b-1 software defined radio receiver featuring gpu accelerators: up to 1000x with respect to cpu implementation. in 2022 9 International Workshop on Tracking, Telemetry and Command Systems for Space Applications (TTC). IEEE, 2022, pp. 1 8.[14] CCSDS 130.11-G-1 Informational Report, SCCC - Summary of Definition and Performance, 2019. [15] S. Asano, T. Maruyama, and Y. Yamaguchi, Performance comparison of fpga, gpu and cpu in image processing, in 2009 international conference on field programmable logic and applications. IEEE, 2009, pp. 126 131. [16] S. Mittal and J. S. Vetter, A survey of cpu-gpu heterogeneous computing techniques, ACM Computing Surveys (CSUR), vol. 47, no. 4, pp. 1 35, 2015. [17] G. Teodoro, R. Sachetto, O. Sertel, M. N. Gurcan, W. Meira, U. Catalyurek, and R. Ferreira, Coordinating the use of gpu and cpu for improving performance of compute intensive applications, in 2009 IEEE International Conference on Cluster Computing and Workshops. IEEE, 2009, pp. 1 10. [18] Nvidia, Nvidia quadro rtx 4000, data sheet, Online https://www.nvidia.com/content/dam/en-zz/Solutions/designvisualization/quadro-product-literature/quadro-rtx-4000-data-sheetus-nvidia-830682- r6-web.pdf. [19] C. Nvidia and F. Fitzek, Cuda, Online http://www.nvidia.com/object/cuda home new, vol. 15, 2006. [20] D. Kirk et al., Nvidia cuda software and gpu parallel computing architecture, in ISMM, vol. 7, 2007, pp. 103 104. [21] L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, Optimal decoding of linear codes for minimizing symbol error rate (corresp.), IEEE Transactions on information theory, vol. 20, no. 2, pp. 284 287, 1974. [22] R. Ciardi, G. Giuffrida, G. Benelli, C. Cardenio, and R. Maderna, Gpu@ sat: A general-purpose programmable accelerator for on board data processing and satellite autonomy, in International Conference on Applied Intelligence and Informatics. Springer, 2022, pp. 35 47 EDHPC 2023 Roberto Ciardi University of Pisa