DARE180U Platform Enhancements in Release 5.6 - AMICSA 2018
The DARE180U platform introduces radiation-hardened ASIC design capabilities on UMC 0.18μm CMOS technology for space and high-energy physics applications. Supported by ESA and featuring ITAR-free components, it offers libraries, IP, and design services for front-end and back-end design flow. The platform history includes key milestones from 2002 to 2018, culminating in Release 5.6 with updates like the calibrated ELT model and analog-on-top design support. These advancements provide accurate modeling and design tools for efficient chip development. Platform improvements aim to meet the demands of cutting-edge aerospace and technology industries.
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DARE180U PLATFORM IMPROVEMENTS IN RELEASE 5.6 GIANCARLO FRANCISCATTO AMICSA 2018
OUTLINE Introduction Design flow History Platform updates Libraries and IP Future work 2 AMICSA 2018
DARE180U PLATFORM INTRODUCTION Radiation hardened ASIC design platform Commercial UMC 0.18 m CMOS technology Space and high-energy physics applications up to 1 Mrad Supported by ESA ITAR free components DARE library DARE180U platform Libraries, IP and design services 3 AMICSA 2018
DARE180U PLATFORM DESIGN FLOW RTL Netlist DARE180U Libraries Front-end design Optional service provided by imec IC-link DARE180U IP Back-end design imec IC-link only rad hard design verification Third-party IP Fabrication Optional support services provided by imec IC-link Assembly Test & Qualification 4 AMICSA 2018
DARE180U PLATFORM HISTORY 2002 2010 2011 2013 2017 2018 Release 5.6 (imec) Release 1.0 (ESA) CORE I/O SRAM LVDS PLL DARE+ project (ESA) Release 5.5 Release 4.1 First flight models KNUT chip (TESAT) TRL-9 status achievement Hispasat36W-1 satellite launch KNUT chip + antenna chip (Arquimea) 5 AMICSA 2018
PLATFORM UPDATES ADK CALIBRATED ELT MODEL DARE180U ADK ELT Pcell + simulation models + verification and extraction rules Equivalent W/L CERN model Good fit for drive strength Underestimates gate capacitances ( W*L) for small transistors Assumes symmetric drain/source overlap capacitances Improvements in version 5.6 Validated equivalent W/L with test measurements Accurate for NMOS -5% deviation for PMOS with small B and H Gate channel and overlap capacitances calculation based on inner/outer geometries 7 AMICSA 2018
PLATFORM UPDATES ANALOG-ON-TOP DESIGN SUPPORT Aid customer IP design using DARE180U library building blocks Full layout cell replacement and radiation/physical verification done by imec Delivered views OpenAccess symbols for schematic design Encrypted netlists for simulation Abstracts and netlists for black-box LVS 8 AMICSA 2018
LIBRARIES AND IP SUMMARY CORE library I/O library LVDS library Bond pad library (new in 5.6) SRAM compiler Other IP (PLL, ADC, POR...) later 10 AMICSA 2018
LIBRARIES AND IP CORE LIBRARY SEU hardened sequential cells SET hardened cells for asynchronous and clock trees Regular combinational cells for data paths New in version 5.6 Optimized cell layouts for sensitive area Added SET-hardened voter cell for TMR support (60 MeV.cm2/mg) New timing characterization data Calibrated ELT model slower PMOS + higher gate capacitance ~ 10% delay degradation 11 AMICSA 2018
LIBRARIES AND IP CORE LIBRARY Layout optimization for sensitive area Using outer diffusion nodes for less critical nodes More efficient ELT aspect ratio Chip Design # Cells Area v.5.5 Area v.5.6 Difference A 377769 40.146 mm2 39.803 mm2 -0.85% B 206548 20.994 mm2 20.904 mm2 -0.43% C 195267 14.819 mm2 14.634 mm2 -1.25% 12 AMICSA 2018
LIBRARIES AND IP I/O AND LVDS LIBRARIES 3.3V digital and analog I/O Standard LVDS receiver and driver cells Support to multi-domain I/O rings New in version 5.6 Extended support to multi-domain I/O rings New breaker cell types Better support for analog and mixed-signal New 1.8V analog I/O and supply cells isolated 1.8V analog I/O domains New 3.3V analog I/O cell variants Improved reliability through better metallization 13 AMICSA 2018
LIBRARIES AND IP BOND PAD LIBRARY Previously distributed in I/O and LVDS libraries New separate library in version 5.6 New bond pad opening size options Added IP specific double bond pad cells Reduced parasitic capacitance by 40% 14 AMICSA 2018
LIBRARIES AND IP SRAM COMPILER Single and dual port blocks 256 to 256K bits Write-mask option Bit interleaving 4, 8, 16, 32 or 64 MBU immunity SEU insensitive possible with EDAC New in version 5.6 Optimized top-level supply routing Better decoupling and reliability New timing characterization data with calibrated ELT model 15 AMICSA 2018
FUTURE WORK VERSION 5.7 1.8V digital I/O cells Distributed Power-On Control GPIO cells LVDS cold-spare and failsafe 17 AMICSA 2018
Hispasat36W-1 launch Kourou, French Guyana January 28th, 2017 QUESTIONS? DARE_SUPPORT@IMEC.BE
