Y86-64 Instruction Set and Hardware Control Language

Delve into the Y86-64 instruction set architecture, exploring sequential architecture implementations for computer architecture. Uncover the various instruction sets and their functionalities, such as halt, nop, call, ret, and more. Additionally, discover the building blocks of hardware, including ALU, combinational logic, MUX, storage elements, and clock operations. Lastly, explore the basics of a hardware control language for expressing limited aspects of hardware operations using boolean and integer data types.

• Y86-64 Instruction Set
• Computer Architecture
• Hardware Control Language
• Building Blocks
• Sequential Architecture

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1. Sequential Architecture Implementation CSCI 370: Computer Architecture

2. Y86-64 Instruction Set #1 6 7 8 9 0 1 2 3 4 5 Byte halt 0 0 nop 1 0 2 cmovXX rA, rB fn rA rB 3 0 F irmovq V, rB rB V 4 0 rmmovq rA, D(rB) rA rB D 5 0 mrmovq D(rB), rA rA rB D 6 OPq rA, rB fn rA rB 7 jXX Dest fn Dest 8 0 call Dest Dest ret 9 0 A 0 rA F pushq rA B 0 rA F popq rA

3. Y86-64 Instruction Set #2 rrmovq 7 0 6 7 8 9 0 1 2 3 4 5 Byte cmovle 7 1 halt 0 0 cmovl 7 2 nop 1 0 cmove 7 3 2 cmovXX rA, rB fn rA rB cmovne 7 4 3 0 F irmovq V, rB rB V cmovge 7 5 4 0 rmmovq rA, D(rB) rA rB D cmovg 7 6 5 0 mrmovq D(rB), rA rA rB D 6 OPq rA, rB fn rA rB 7 jXX Dest fn Dest 8 0 call Dest Dest ret 9 0 A 0 rA F pushq rA B 0 rA F popq rA

4. Y86-64 Instruction Set #3 0 1 6 7 8 9 2 3 4 5 Byte halt 0 0 nop 1 0 2 cmovXX rA, rB fn rA rB 3 0 F irmovq V, rB rB V 4 0 rmmovq rA, D(rB) rA rB D addq 6 0 5 0 mrmovq D(rB), rA rA rB D subq 6 1 6 OPq rA, rB fn rA rB andq 6 2 7 jXX Dest fn Dest xorq 6 3 8 0 call Dest Dest ret 9 0 A 0 rA F pushq rA B 0 rA F popq rA

5. Y86-64 Instruction Set #4 6 7 8 jmp 9 7 0 0 1 2 3 4 5 Byte halt 0 0 jle 7 1 nop 1 0 jl 7 2 2 cmovXX rA, rB fn rA rB je 7 3 3 0 F irmovq V, rB rB V jne 7 4 4 0 rmmovq rA, D(rB) rA rB D jge 7 5 5 0 mrmovq D(rB), rA rA rB D jg 7 6 6 OPq rA, rB fn rA rB 7 jXX Dest fn Dest 8 0 call Dest Dest ret 9 0 A 0 rA F pushq rA B 0 rA F popq rA

6. Building Blocks fun A = A L U Combinational Logic Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control B 0 MUX 1 Storage Elements Store bits Addressable memories Non-addressable registers Loaded only as clock rises valA A srcA valW Register file W dstW valB B srcB Clock Clock

7. Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool: Boolean a, b, c, int: words A, B, C, Does not specify word size---bytes, 32-bit words, Statements bool a = bool-expr ; int A = int-expr ;

8. HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a && b, a || b, !a Word Comparisons A == B, A != B, A < B, A <= B, A >= B, A > B Set Membership A in { B, C, D } Same as A == B || A == C || A == D Word Expressions Case expressions [ a : A; b : B; c : C ] Evaluate test expressions a, b, c, in sequence Return word expression A, B, C, for first successful test

9. SEQ Hardware Structure State Program counter register (PC) Condition code register (CC) Register File Memories Access same memory space Data: for reading/writing program data Instruction: for reading instructions Instruction Flow Read instruction at address specified by PC Process through stages Update program counter

10. SEQ Stages Fetch Read instruction from instruction memory Decode Read program registers Execute Compute value or address Memory Read or write data Write Back Write program registers PC Update program counter

11. Instruction Decoding Optional Optional 5 0 rA rB D icode ifun rA rB valC Instruction Format Instruction byte Optional register byte Optional constant word icode:ifun rA:rB valC

12. Executing Arith./Logical Operation 6 OPq rA, rB fn rA rB Fetch Memory Do nothing Write back Update register PC Update Increment PC by 2 Read 2 bytes Decode Read operand registers Execute Perform operation Set condition codes

13. Stage Computation: Arith/Log. Ops OPq rA, rB icode:ifun M1[PC] rA:rB M1[PC+1] Read instruction byte Read register byte Fetch valP PC+2 valA R[rA] valB R[rB] valE valB OP valA Set CC Compute next PC Read operand A Decode Read operand B Perform ALU operation Execute Set condition code register Memory Write R[rB] valE Write back result back PC update PC valP Update PC Formulate instruction execution as sequence of simple steps Use same general form for all instructions

14. Executing rmmovq 4 0 rA rB D rmmovq rA, D(rB) Fetch Memory Write to memory Write back Do nothing PC Update Increment PC by 10 Read 10 bytes Decode Read operand registers Execute Compute effective address

15. Stage Computation: rmmovq rmmovq rA, D(rB) icode:ifun M1[PC] rA:rB M1[PC+1] valC M8[PC+2] valP PC+10 valA R[rA] valB R[rB] valE valB + valC Read instruction byte Read register byte Fetch Read displacement D Compute next PC Read operand A Decode Read operand B Compute effective address Execute M8[valE] valA Memory Write Write value to memory back PC update PC valP Update PC Use ALU for address computation

16. Executing popq b 0 rA 8 popq rA Fetch Memory Read from old stack pointer Write back Update stack pointer Write result to register PC Update Increment PC by 2 Read 2 bytes Decode Read stack pointer Execute Increment stack pointer by 8

17. Stage Computation: popq popq rA icode:ifun M1[PC] rA:rB M1[PC+1] Fetch Read instruction byte Read register byte valP PC+2 valA R[%rsp] valB R[%rsp] valE valB + 8 Compute next PC Read stack pointer Decode Read stack pointer Increment stack pointer Execute valM M8[valA] R[%rsp] valE R[rA] valM PC valP Memory Write Read from stack Update stack pointer Write back result back PC update Update PC Use ALU to increment stack pointer Must update two registers Popped value New stack pointer

18. Executing Conditional Moves 2 cmovXX rA, rB fn rA rB Fetch Memory Do nothing Write back Update register (or not) PC Update Increment PC by 2 Read 2 bytes Decode Read operand registers Execute If !cnd, then set destination register to 0xF

19. Stage Computation: Cond. Move cmovXX rA, rB icode:ifun M1[PC] rA:rB M1[PC+1] Read instruction byte Read register byte Fetch valP PC+2 valA R[rA] valB 0 valE valB + valA If ! Cond(CC,ifun) rB 0xF Compute next PC Read operand A Decode Pass valA through ALU Execute (Disable register update) Memory Write R[rB] valE Write back result back PC update PC valP Update PC Read register rA and pass through ALU Cancel move by setting destination register to 0xF If condition codes & move condition indicate no move

20. Executing Jumps 7 jXX Dest fn Dest Not taken XX XX fall thru: XX XX target: Taken Fetch Memory Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch Read 9 bytes Increment PC by 9 Decode Do nothing Execute Determine whether to take branch based on jump condition and condition codes

21. Stage Computation: Jumps jXX Dest icode:ifun M1[PC] Read instruction byte Fetch valC M8[PC+1] valP PC+9 Read destination address Fall through address Decode Execute Cnd Cond(CC,ifun) Take branch? Memory Write back PC update PC Cnd ? valC : valP Update PC Compute both addresses Choose based on setting of condition codes and branch condition

22. Executing call 8 0 Dest call Dest XX XX return: XX XX target: Fetch Memory Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest Read 9 bytes Increment PC by 9 Decode Read stack pointer Execute Decrement stack pointer by 8

23. Stage Computation: call call Dest icode:ifun M1[PC] Read instruction byte Fetch valC M8[PC+1] valP PC+9 Read destination address Compute return point Decode valB R[%rsp] valE valB + 8 Read stack pointer Decrement stack pointer Execute M8[valE] valP R[%rsp] valE Memory Write Write return value on stack Update stack pointer back PC update PC valC Set PC to destination Use ALU to decrement stack pointer Store incremented PC

24. Executing ret 9 0 ret XX XX return: Fetch Memory Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address Read 1 byte Decode Read stack pointer Execute Increment stack pointer by 8

25. Stage Computation: ret ret icode:ifun M1[PC] Read instruction byte Fetch valA R[%rsp] valB R[%rsp] valE valB + 8 Read operand stack pointer Decode Read operand stack pointer Increment stack pointer Execute valM M8[valA] R[%rsp] valE Memory Write Read return address Update stack pointer back PC update PC valM Set PC to return address Use ALU to increment stack pointer Read return address from memory

26. Computation Steps OPq rA, rB icode:ifun M1[PC] rA:rB M1[PC+1] icode,ifun Read instruction byte rA,rB Read register byte Fetch valC [Read constant word] valP PC+2 valA R[rA] valB R[rB] valE valB OP valA Set CC valP Compute next PC valA, srcA Read operand A Decode valB, srcB Read operand B valE Perform ALU operation Execute Cond code Set/use cond. code reg Memory Write valM [Memory read/write] R[rB] valE dstE Write back ALU result dstM [Write back memory result] back PC update PC valP PC Update PC All instructions follow same general pattern Differ in what gets computed on each step

27. Computation Steps call Dest icode:ifun M1[PC] icode,ifun Read instruction byte rA,rB [Read register byte] Fetch valC M8[PC+1] valP PC+9 valC Read constant word valP Compute next PC valA, srcA [Read operand A] Decode valB R[%rsp] valE valB + 8 valB, srcB Read operand B valE Perform ALU operation Execute Cond code [Set /use cond. code reg] M8[valE] valP R[%rsp] valE Memory Write valM Memory read/write dstE Write back ALU result dstM [Write back memory result] back PC update PC valC PC Update PC All instructions follow same general pattern Differ in what gets computed on each step

28. Computed Values Fetch Execute valE Cnd Memory valM icode ifun rA rB valC valP Instruction code Instruction function Instr. Register A Instr. Register B Instruction constant Incremented PC ALU result Branch/move flag Value from memory Decode srcA srcB dstE dstM valA valB Register ID A Register ID B Destination Register E Destination Register M Register value A Register value B

29. SEQ Hardware Blue boxes predesigned hardware blocks E.g., memories, ALU Gray boxes control logic Describe in HCL White ovals labels for signals Thick lines 64-bit word values Thin lines 4-8 bit values Dotted lines 1-bit values

30. Fetch Logic Predefined Blocks PC: Register containing PC Instruction memory: Read 10 bytes (PC to PC+9) Signal invalid address Split: Divide instruction byte into icode and ifun Align: Get fields for rA, rB, and valC

31. Fetch Logic Control Logic Instr. Valid: Is this instruction valid? icode, ifun: Generate no-op if invalid address Need regids: Does this instruction have a register byte? Need valC: Does this instruction have a constant word?

32. Fetch Control Logic in HCL icode ifun Split Byte 0 Instruction memory # Determine instruction code int icode = [ imem_error: INOP; 1: imem_icode; ]; imem_error PC # Determine instruction function int ifun = [ imem_error: FNONE; 1: imem_ifun; ];

33. Fetch Control Logic in HCL halt 0 0 nop 1 0 2 cmovXX rA, rB fn rA rB 3 0 8 irmovq V, rB rB V 4 0 rmmovq rA, D(rB) rA rB D 5 0 mrmovq D(rB), rA rA rB D 6 OPq rA, rB fn rA rB 7 jXX Dest fn Dest 8 0 call Dest Dest ret 9 0 A 0 rA F popq rA B 0 rA F popq rA bool need_regids = icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, IIRMOVQ, IRMMOVQ, IMRMOVQ }; bool instr_valid = icode in { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ, IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };

34. Decode Logic Register File Read ports A, B Write ports E, M Addresses are register IDs or 15 (0xF) (no access) Control Logic srcA, srcB: read port addresses dstE, dstM: write port addresses Signals Cnd: Indicate whether or not to perform conditional move Computed in Execute stage

35. OPq rA, rB valA R[rA] Decode Read operand A A Src. cmovXX rA, rB valA R[rA] Decode Read operand A rmmovq rA, D(rB) valA R[rA] Decode Read operand A popq rA valA R[%rsp] Decode Read stack pointer jXX Dest Decode No operand call Dest Decode No operand ret valA R[%rsp] Decode Read stack pointer int srcA = [ ]; icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : rA; icode in { IPOPQ, IRET } : RRSP; 1 : RNONE; # Don't need register

36. OPq rA, rB R[rB] valE Write-back Write back result E Dest. cmovXX rA, rB Conditionally write back result R[rB] valE Write-back rmmovq rA, D(rB) Write-back None popq rA R[%rsp] valE Write-back Update stack pointer jXX Dest Write-back None call Dest R[%rsp] valE Write-back Update stack pointer ret R[%rsp] valE Write-back Update stack pointer int dstE = [ ]; icode in { IRRMOVQ } && Cnd : rB; icode in { IIRMOVQ, IOPQ} : rB; icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP; 1 : RNONE; # Don't write any register

37. Execute Logic Units ALU Implements 4 required functions Generates condition code values CC Register with 3 condition code bits cond Computes conditional jump/move flag Control Logic Set CC: Should condition code register be loaded? ALU A: Input A to ALU ALU B: Input B to ALU ALU fun: What function should ALU compute?

38. ALU A Input OPq rA, rB valE valB OP valA Execute Perform ALU operation cmovXX rA, rB valE 0 + valA Execute Pass valA through ALU rmmovq rA, D(rB) valE valB + valC Execute Compute effective address popq rA valE valB + 8 Execute Increment stack pointer jXX Dest Execute No operation call Dest valE valB + 8 Execute Decrement stack pointer ret valE valB + 8 Execute Increment stack pointer int aluA = [ ]; icode in { IRRMOVQ, IOPQ } : valA; icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : valC; icode in { ICALL, IPUSHQ } : -8; icode in { IRET, IPOPQ } : 8; # Other instructions don't need ALU

39. OPl rA, rB valE valB OP valA Execute ALU Op. Perform ALU operation cmovXX rA, rB valE 0 + valA Execute Pass valA through ALU rmmovl rA, D(rB) valE valB + valC Execute Compute effective address popq rA valE valB + 8 Execute Increment stack pointer jXX Dest Execute No operation call Dest valE valB + 8 Execute Decrement stack pointer ret valE valB + 8 Execute Increment stack pointer int alufun = [ ]; icode == IOPQ : ifun; 1 : ALUADD;

40. Memory Logic Memory Reads or writes memory word Control Logic stat: What is instruction status? Mem. read: should word be read? Mem. write: should word be written? Mem. addr.: Select address Mem. data.: Select data

41. Instruction Status Control Logic stat: What is instruction status? ## Determine instruction status int Stat = [ imem_error || dmem_error : SADR; !instr_valid: SINS; icode == IHALT : SHLT; 1 : SAOK; ];

42. Memory Address OPq rA, rB Memory No operation rmmovq rA, D(rB) M8[valE] valA Memory Write value to memory popq rA valM M8[valA] Memory Read from stack jXX Dest Memory No operation call Dest M8[valE] valP Memory Write return value on stack ret valM M8[valA] Memory Read return address int mem_addr = [ icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE; icode in { IPOPQ, IRET } : valA; # Other instructions don't need address ];

43. Memory Read OPq rA, rB Memory No operation rmmovq rA, D(rB) M8[valE] valA Memory Write value to memory popq rA valM M8[valA] Memory Read from stack jXX Dest Memory No operation call Dest M8[valE] valP Memory Write return value on stack ret valM M8[valA] Memory Read return address bool mem_read = icode in { IMRMOVQ, IPOPQ, IRET };

44. PC Update Logic New PC Select next value of PC

45. OPq rA, rB PC valP PC Update PC update Update PC rmmovq rA, D(rB) PC valP PC update Update PC popq rA PC valP PC update Update PC jXX Dest PC Cnd ? valC : valP PC update Update PC call Dest PC valC PC update Set PC to destination ret PC valM PC update Set PC to return address int new_pc = [ ]; icode == ICALL : valC; icode == IJXX && Cnd : valC; icode == IRET : valM; 1 : valP;

46. SEQ Operation State PC register Cond. Code register Data memory Register file All updated as clock rises Combinational Logic ALU Control logic Memory reads Instruction memory Register file Data memory

47. SEQ Op @1 state set according to second irmovq instruction combinational logic starting to react to state changes

48. SEQ Op @2 state set according to second irmovq instruction combinational logic generates results for addq instruction

49. SEQ Op @3 state set according to addq instruction combinational logic starting to react to state changes

50. SEQ Op @4 state set according to addq instruction combinational logic generates results for je instruction

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