Understanding Phase Determinism Study Meeting Presentation
This presentation covers various aspects of phase stability, reproducibility, and determinism in TCLink architecture. It includes open questions regarding temperature variations, performance relationships, clock synchronization, stability enhancements, and architectural considerations. Detailed outlines, principles, configurations, and differences between master and slave components in the TCLink system are discussed, aiming to address current performance and future development needs.
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Presentation Transcript
Phase Determinism Study Meeting Introduction S. Baron, E. Mendes 2/16/2022 1
Open questions in 2021 1. What is the phase stability/reproducibility/determinism of one TCLink In open loop/ closed loop ? At stable / varying temperature ? Considering std or pkpk phase ? 2. What is the relationship between single/ cascaded link in terms of performance? 3. Is the DDMTD measurement on TCLink Master FPGA representative of the phase of the recovered clock at the TCLink Slave FPGA? 4. Could we gain additional stability by playing with transceivers, parameters, clocks, etc? 5. Are there other architecture choices which could potentially propose better performance? 6. Is the current TCLink performance compatible with the requirements (temperature, phase reproducibility) of the experiments? 2/16/2022 2
Outline TCLink architecture (reminder) Studies Single Link Cascaded Link Conclusions Discussion Answering some of the Open Questions Opening some new ones Next Steps 2/16/2022 3
TCLink Principle in 1 slide IPs developped for Xilinx Ultrascale and Ultrascale+ Only Tested on GTH and GTY transceivers Master IP Slave IP The configuration of each transceiver has been carefully chosen to match TCLink requirements (see next slide) 2/16/2022 4
MASTER and SLAVE Tx Both Tx have exaclty the same configuration FIFO enabled FIFO half-full Flag used to adjust Phase Interpolator Tx PI controlled by the firmware to keep FIFO flag toggling 1.5ps step 2/16/2022 5
MASTER and SLAVE Tx QPLL used TxPLLRefClkDiv1 Delay Aligner Bypassed TxOUTCLK used for user logic 2/16/2022 6
MASTER and SLAVE Rx Same principle but some differences Both have: Buffer Bypass (fixed latency for both directions) Although not mandatory for upstream rxDelayAligner enabled mandatory by Xilinx in Buffer Bypass mode RxoutclkPMA used 2/16/2022 7 the differences mostly reside in the RxSlide Mode for phase and data alignment
MASTER and SLAVE Tx Differences MASTER SLAVE rxSlide PCS mode Xilinx recommended scheme PCS mode only shifts the data rxSlide PMA mode Not recommended by Xilinx, forced by an XDC constraints PMA mode shifts both the clock and the data Extensively tested (also used in the PON, the GBT-FPGA ) Clock Alignment: Rxusrclk is not recovered with fixed phase, but phase has to be known for DDMTD (in UI) Use the rxslide pulses to account the phase difference (in UI) between txusrclk and rxusrclk at startup and adjust the control loop offset Clock Alignment: Clock and data are shifted to ensure frame alignment AND rxusrclk fixed-phase recovery Clock shifted by 2UI every other rxslide pulse. A reset is implemented in the odd case. Two fall back solutions in case of problem with this implementation Roulette approach (reset MGT until the header is aligned) Buffer bypass in PCS mode (only data are shifted), count the rxslide pulses and compensate with external MMCM (not tested but close to the way the Master Rx is implemented) 2/16/2022 8
Outline TCLink architecture (reminder) Studies Single Link Cascaded Link Conclusions Discussion Answering some of the Open Questions Opening some new ones Next Steps 2/16/2022 9
