Time Synchronization
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Introduction
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RX-TX 1588 CPTS Time Stamping
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Managing CPTS 32-Bit Timer
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Small Cell Time Sync Implementation
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Q&A
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Keystone 2 Devices support the IEEE 1588v2 standard through the
Ethernet sub-systems.
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Keystone 2 devices provide two Ethernet sub-systems (1G & 10G).
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Both support Annex D (IPV4), E (IPV6) and F (802.3)
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Both Ethernet sub-systems utilize the following modules for 1588
operation.
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CPSW - Common Platform Switch Subsystem
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CPTS - Common Platform Time Sync Module
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CPTS on KS2 devices supports additional time synchronization features such as
precisely-timed output pulses (TS_COMP/TS_SYNC). It can also timestamp hard
signals such as GPS 1pps (via HW_TS_PUSH).
*KS2 Only
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CPTS Reference Clock
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CPTS Hardware Push Events
Note- There is some swapping in events 3-6 when compared with the Kepler Architecture Spec. As this can be handled with software,
it is not an issue
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CPTS syncE rxbclk connections
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CPTS TSRXCLKOUT(0/1)(N/P)
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CPTS Time Stamps all RX PKTS upon Start of Frame Delimiter (SFD) crossing the MAC interface
(on any of the four Ethernet lanes). CPSW 1588 Decoder establishes if it is a valid PTP packet and
signals CPTS to push the TS into the Event FIFO
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CPTS Time Stamps TX PKTS upon SFD crosses CPGMAC. CPSW 1588 Decoder establishes if it
is a valid PTP packet and signals CPTS to push the TS into the Event FIFO
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Example for 1588 PTP Time:
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CPTS Time Before Rollover Event
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CPTS Time After Rollover Event
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As the 1588 decoder takes some time to validate a packet it can happen that a
PTP packet is timestamped just before a rollover event, but the rollover event is
pushed into the EVENT FIFO first.
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This allows the software to determine after a rollover event if the following
PTP_TS happened after or before the rollover.
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Events on Real Timeline
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Events on FIFO
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To solve this issue software checks the MSB of the PTP_TS between a rollover
event and a half-rollover event.
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If it is 1, it happened before the rollover event. Thus the upper 32-bit CPTS time
needs to be decremented for this timestamp.
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If it is 0 it happened after the rollover event.
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We have discussed how CPTS 32-bit
timer is maintained as a 64-bit clock. But,
how to maintain 1588 epoch time?
(nanoseconds).
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For this, 1588 Stack uses Linux System
time. This time is driven in KS2 by the
A15 ARM core timer.
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To properly convert CPTS tick time to
nanoseconds the 1588 stack calibrates
system time by computing the offset
between the CPTS timer and the A15
timer.
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It uses TS_PUSH capability to read the
CPTS timer.
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More details on the 1588 stack in the next
section.
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A complete 1588 clock sync solution consists of the following blocks.
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The network driver matches up PTP packets with the time stamps from the CPTS. Linux
socket interface calls are used to retrieve the packet data and the time stamps.
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The 1588 stack encodes PTP transmit packets and parses PTP receive packets.
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The PTP clock sync application
performs packet delay variation
filtering. It computes the frequency
and time offsets between master
time server clock and local clock.
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Timestamp data provided in CPTS
raw time.
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Annex E and D support at CPTS.
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Linux PTP Socket listens only to
CPTS event. No Need for PA.
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The system clock sync application
uses the computed frequency and
time offsets as inputs to a
software digital phase locked loop.
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That DPLL computes DAC voltage
updates to lock the VCXO
frequency to the master time
server
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SPI write done by ARM.
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No DSP needed.
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During system start up the OCXO will
stabilize and clocks will become
available to CPTS
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At this point the CPTS driver will enable
the input clock by writing the chip level
register CPTS_RFTCLK_SEL.
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Please refer to your device datasheet for
specific value details.
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By default the CPTS driver will initialize
the ENET Switch and CPTS for Annex
D & E unicast support with VLAN
ethertype of 0x8100.
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To change default values via SYSF and
configurable parameters please refer to
attached cpts_driver.txt section A.3
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For more details on CPTS driver
responsibilities please refer to attached
cpts_driver.txt section B and go to
http://processors.wiki.ti.com/index.php/
MCSDK_UG_Chapter_Exploring#Com
mon_Platform_Time_Sync_.28CPTS.29
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As mentioned in the platform overview the
1588 app (PTP Stack, PTP Clock Sync
App, System Clock Sync App) is
responsible of adjusting the CPTS
reference clock frequency
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However, the 1588 must forward the
frequency adjustment to the CPTS driver
using the clock_adjtime API with a flag
ADJ_FREQUENCY
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This is needed for CPTS driver to calculate
UCT time correctly.
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If any absolute (UCT) time adjustments
must be made the 1588 app can use the
clock_settime function.
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For more details refer to the attached file
cpts_driver.txt section C.
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Once the clock sync app calibrates CPTS clock it can program CPTS to
generate the 1pps to AIF. However, the master Sync packets can be lost for a
period of time.
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When this happens the local clock can drift from the master time.
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DPLL software needs to determine if it needs re-synchronization.
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Along with the DPLL SW the Clock Sync App needs a state machine to
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perform initial synchronization,
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generate output pulse,
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keep frequency and time locked to master time,
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hold frequency during master signal loss,
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Re-establish synchronization upon signal return.
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In the next few slides the state machine and DPLL algorithm will be
explained.
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The 5 states of the DPLL Software State Machine
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During Initial Lock DPLL SW tracks the
master time over a period of time.
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Master sync pulses carry the egress
time in the PTP packet.
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Sync packets are time stamped on
arrival by CPTS.
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Delay_req packets are sent to the
Master time server while time
stamped at egress.
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Master responds with a
Delay_response carrying the arrival
time of Delay_req.
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DPLL SW filters these four
timestamps for network delay
variations and uses them as inputs
to output a control voltage step to the
DAC through the SPI interface.
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Once DPLL software has calibrated
the local slave clock (i.e. CPTS timer)
to the master time server. It can safely
determine the absolute time 1 second
boundary.
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The clock sync application then
computes a CPTS time tick value in
the future that equates a 1 second
period.
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This value is loaded in the compare
register of CPTS. When CPTS timer
reaches this value it generates the 1pps
pulse.
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The process is repeated to maintain a
1pps output pulse to AIF.
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Once the 1pps has been generated the AIF is
synchronized to absolute time with the master time
server.
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Software keeps going back to the Sync Output state to load
the CPTS compare register with the next value for the 1pps.
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The DPLL software needs to keep tracking the master
clock to keep the local frequency in lock with the master
frequency.
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For this the DPLL software needs PTP sync pulses from
the master time.
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The slave to master path time can be estimated with enough
precision to lock the frequency so delay_req/delay_resp
packets are needed less frequently.
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To estimate the arrival time the PTP clock sync app
filters network impairments due to transit time variations
of PTP Sync packets.
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In the holdover state the voltage output to the
DAC is held constant.
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The PTP capture events are monitored to see if
the signal has returned.
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When PTP packets are captured DPLL software
can determine how much drift has occurred in
the local clock.
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If drift is too much re-sync state is entered.
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Else In-Lock state is entered.
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In some situations the drift might have caused
the antenna to lose absolute time reference.
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Initial Lock is state is entered to re-calibrate
CPTS timer and generate another sync
pulse to the AIF.
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The Re-sync state is entered
because the radio frame
timing has drifted outside of
the specified timing window.
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The DPLL algorithm slowly
re-calibrates the local clock
and locks the frequency to
the master clock frequency.
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Time synchronization with GPS 1pps
signal is almost identical to IEEE 1588
time synchronization.
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The primary difference being that CPTS
events to the GPS SW are generated by
time stamping the 1pps signal through the
TS_HW_PUSH events.
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The GPS state machine in the clock sync
application has the same 5 states as the
1588 state machine.
Introduction to time synchronization with Keystone 2 devices supporting IEEE 1588v2 standard through Ethernet sub-systems, providing precise timing features and hardware signal timestamping capabilities. Explore CPTS block diagram, events on KS2, NETCP CPTS connections, RX-TX 1588 CPTS time stamping, and more in this detailed overview.
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Presentation Transcript
Time Synchronization Keystone 2 Devices 1
Overview Introduction RX-TX 1588 CPTS Time Stamping Managing CPTS 32-Bit Timer Small Cell Time Sync Implementation Q&A 2
Introduction Keystone 2 Devices support the IEEE 1588v2 standard through the Ethernet sub-systems. Keystone 2 devices provide two Ethernet sub-systems (1G & 10G). Both support Annex D (IPV4), E (IPV6) and F (802.3) Both Ethernet sub-systems utilize the following modules for 1588 operation. CPSW - Common Platform Switch Subsystem CPTS - Common Platform Time Sync Module 4
CPTS Block Diagram CPTS on KS2 devices supports additional time synchronization features such as precisely-timed output pulses (TS_COMP/TS_SYNC). It can also timestamp hard signals such as GPS 1pps (via HW_TS_PUSH). *KS2 Only 5
NETCP CPTS CONNECTIONS CPTS Reference Clock Mux Sel Value Reference Clock Followed 0 1 2 3 8 Clk2 Clk3 Timi0 Timi1 Tsrefclk CPTS Hardware Push Events Event Number 1 2 3 4 5 6 7 8 Connection syncE XGE sync Tspushevt1 Tspushevt0 Timi1 Timi0 Reserved Reserved Note- There is some swapping in events 3-6 when compared with the Kepler Architecture Spec. As this can be handled with software, it is not an issue
NETCP CPTS CONNECTIONS (Contd) CPTS syncE rxbclk connections Mux Sel Value 0 1 2 3 Connection Rxbclk[0] Rxbclk[1] Rxbclk[2] Rxbclk[3] CPTS TSRXCLKOUT(0/1)(N/P) Mux Sel Value TSRXCLKOUT0(N/P) TSRXCLK1(N/P) 00 Rxbclk[0] Rxbclk[0] 11 Rxbclk[1] Rxbclk[1] 22 Rxbclk[2] Rxbclk[2] 33 Rxbclk[3] Rxbclk[3]
CPTS 1588 RX Time Stamping CPTS Time Stamps all RX PKTS upon Start of Frame Delimiter (SFD) crossing the MAC interface (on any of the four Ethernet lanes). CPSW 1588 Decoder establishes if it is a valid PTP packet and signals CPTS to push the TS into the Event FIFO 1) RX PTP PKT CPSW (Ethernet Swtich) 4) MAC/IP Header ENET 1588 DECODER Annex (D, E & F) MAC Ports (0-3) 5) VALID PTP PKT 2) SFD of PTP PKT CPTS 3) PTP PKT Time Stamped 6) PUSH TS TO EVENT FIFO EVENT FIFO ... ... ... ... Future Event Prev EVENT PTP_TS (6)
CPTS 1588 TX Time Stamping CPTS Time Stamps TX PKTS upon SFD crosses CPGMAC. CPSW 1588 Decoder establishes if it is a valid PTP packet and signals CPTS to push the TS into the Event FIFO 1) TX PTP PKT 2) MAC/IP Header CPSW (Ethernet Switch) CPPI PORT ALE ENET 1588 DECODER (Annex D, E & F) MAC Ports (0-3) 3) VALID PTP PKT 4) SFD of PTP PKT CPTS 5) PTP PKT Time Stamped 6) PUSH TS TO EVENT FIFO EVENT FIFO ... ... ... ... Future Event Prev EVENT PTP_TS (6)
Rollover Event The CPTS contains a 32-bit time stamp value (time_stamp[31:0]). The counter upper bits are maintained by host software. The rollover event indicates to software that the time_stamp counter has rolled over from 0xFFFF_FFFF to 0x0000_0000 and that software maintained upper count value should be incremented. Example for 1588 PTP Time: CPTS Time Before Rollover Event 32-Bit (MSB) 32-Bit (LSB) 0x00000000 PTP_TIMESTAMP CPTS Time After Rollover Event 32-Bit (MSB) 32-Bit (LSB) 0x00000001 PTP_TIMESTAMP 13
Half-Rollover Event As the 1588 decoder takes some time to validate a packet it can happen that a PTP packet is timestamped just before a rollover event, but the rollover event is pushed into the EVENT FIFO first. The Half-Rollover event indicates to software that the time_stamp counter has rolled over from 0x7FFF_FFFF to 0x8000_0000. This allows the software to determine after a rollover event if the following PTP_TS happened after or before the rollover.
Half-Rollover Event - Example Events on Real Timeline PTP_TS (0x8000FFFF) Half-Rollover Event PTP_TS (0x38001000) PTP_TS (0xEFFFFFF0) Rollover Event Events on FIFO TIME CPTS EVENT FIFO PTP_TS (0x8000FFFF) Half-Rollover Event PTP_TS (0x38001000) PTP_TS (0xEFFFFFF0) ... Future Event Rollover Event
Half-Rollover Event - Example To solve this issue software checks the MSB of the PTP_TS between a rollover event and a half-rollover event. If it is 1, it happened before the rollover event. Thus the upper 32-bit CPTS time needs to be decremented for this timestamp. If it is 0 it happened after the rollover event.
Linux System Time and CPTS Time We have discussed how CPTS 32-bit timer is maintained as a 64-bit clock. But, how to maintain 1588 epoch time? (nanoseconds). ARM Core 3) Compute Offset PTP Stack For this, 1588 Stack uses Linux System time. This time is driven in KS2 by the A15 ARM core timer. CPTS Time LinuxSystem Time (ns) A15 Timer To properly convert CPTS tick time to nanoseconds the 1588 stack calibrates system time by computing the offset between the CPTS timer and the A15 timer. 1) TS_PUSH Write 2) TS_PUSH Event Time Stamp CPTS It uses TS_PUSH capability to read the CPTS timer. More details on the 1588 stack in the next section.
Small Cell Time Sync Implementation 18
IEEE 1588 Overview on Keystone 2 A complete 1588 clock sync solution consists of the following blocks. HW Blocks SW Blocks 1) network driver, 2) 1588 stack, 3) PTP clock sync application 4) system clock sync application 1) CPTS Module 2) External DAC & OCXO The network driver matches up PTP packets with the time stamps from the CPTS. Linux socket interface calls are used to retrieve the packet data and the time stamps. The 1588 stack encodes PTP transmit packets and parses PTP receive packets.
IEEE 1588 Overview on Keystone 2 Platform 1588 Top Level PTP Clock Sync App Linux Socket PTP Packet Listen System Clock Sync App 8 7 The PTP clock sync application performs packet delay variation filtering. It computes the frequency and time offsets between master time server clock and local clock. Timestamp data provided in CPTS raw time. Annex E and D support at CPTS. Linux PTP Socket listens only to CPTS event. No Need for PA. Time stamp data Freq. Offs Time Offs PTP Stack Network Delay Filtering DPLL SW Statistics 9 SPI Freq. Adjust 5 Forward freq adjustment Add Event and TS Data [CPTS & UCT time] to PKT 10 CPTS Driver Match Event to PKT, Retrieve TS DAC 11 4 Write TS_COMP to generate 1 PPS 3 Other clocks Events and Time stamp Data Pkt Data The system clock sync application uses the computed frequency and time offsets as inputs to a software digital phase locked loop. Clock Gen VCXO CPTS PA TSREFCLKP/N 1pps 1 2 Pkt time stamp every SOF delimiter Annex D, E and F decode Pkt Data That DPLL computes DAC voltage updates to lock the VCXO frequency to the master time server SPI write done by ARM. No DSP needed. ENET SW HW Block SW Block Ethernet Packet
IEEE 1588 Overview on Keystone 2 SW HW During system start up the OCXO will stabilize and clocks will become available to CPTS tsrefclk CLKS 1588 APP User Space Linux Socket PTP Packet Listen Kernel Space At this point the CPTS driver will enable the input clock by writing the chip level register CPTS_RFTCLK_SEL. Please refer to your device datasheet for specific value details. CPTS Driver Match Event to PKT, Retrieve TS Hardware By default the CPTS driver will initialize the ENET Switch and CPTS for Annex D & E unicast support with VLAN ethertype of 0x8100. To change default values via SYSF and configurable parameters please refer to attached cpts_driver.txt section A.3 tsrefclk CPTS PA ENET SW For more details on CPTS driver responsibilities please refer to attached cpts_driver.txt section B and go to http://processors.wiki.ti.com/index.php/ MCSDK_UG_Chapter_Exploring#Com mon_Platform_Time_Sync_.28CPTS.29 SW HW
IEEE 1588 Overview on Keystone 2 SW HW Freq. Adjust As mentioned in the platform overview the 1588 app (PTP Stack, PTP Clock Sync App, System Clock Sync App) is responsible of adjusting the CPTS reference clock frequency tsrefclk CLKS 1588 APP TIME/FREQ Management API clock_gettime clock_adjtime clock_settime SYNC or DELAY_REQ PKT User Space Linux Socket PTP Packet Listen Kernel Space 3 Add Event and TS Data [CPTS & UCT time] to PKT However, the 1588 must forward the frequency adjustment to the CPTS driver using the clock_adjtime API with a flag ADJ_FREQUENCY This is needed for CPTS driver to calculate UCT time correctly. CPTS Driver Match Event to PKT, Retrieve TS Hardware 2 Events and Time stamp Data Delay_Req Pkt Sync Pkt tsrefclk CPTS PA If any absolute (UCT) time adjustments must be made the 1588 app can use the clock_settime function. Annex D, E and F decode TS every SOF delimiter 1 1 Pkt Data ENET SW For more details refer to the attached file cpts_driver.txt section C. SW HW SYNC or DELAY_REQ PKT
IEEE 1588 DPLL Software Once the clock sync app calibrates CPTS clock it can program CPTS to generate the 1pps to AIF. However, the master Sync packets can be lost for a period of time. When this happens the local clock can drift from the master time. DPLL software needs to determine if it needs re-synchronization. Along with the DPLL SW the Clock Sync App needs a state machine to 1. perform initial synchronization, 2. generate output pulse, 3. keep frequency and time locked to master time, 4. hold frequency during master signal loss, 5. Re-establish synchronization upon signal return. In the next few slides the state machine and DPLL algorithm will be explained.
IEEE 1588 DPLL Software The 5 states of the DPLL Software State Machine Fast Resync Required Initial Lock Holdover PTP Sync Lost PTP Sync Returns Timing is OK PTP Sync Returns Timing is far off Time Sync Achieved Generate 1pps In Lock Time Sync Achieved Sync Pulse Generated Sync Output Re-sync
IEEE 1588 DPLL SW Initial Lock During Initial Lock DPLL SW tracks the master time over a period of time. Master sync pulses carry the egress time in the PTP packet. Sync packets are time stamped on arrival by CPTS. Delay_req packets are sent to the Master time server while time stamped at egress. Master responds with a Delay_response carrying the arrival time of Delay_req. Fast Resync Required Initial Lock Holdover PTP Sync Lost PTP Sync Returns Timing is OK PTP Sync Returns Timing is far off Time Sync Achieved DPLL SW filters these four timestamps for network delay variations and uses them as inputs to output a control voltage step to the DAC through the SPI interface. Generate 1pps In Lock Time Sync Achieved Sync Pulse Generated Sync Output Re-sync
IEEE 1588 DPLL SW Sync Output Once DPLL software has calibrated the local slave clock (i.e. CPTS timer) to the master time server. It can safely determine the absolute time 1 second boundary. Fast Resync Required Initial Lock Holdover PTP Sync Lost PTP Sync Returns Timing is OK The clock sync application then computes a CPTS time tick value in the future that equates a 1 second period. This value is loaded in the compare register of CPTS. When CPTS timer reaches this value it generates the 1pps pulse. The process is repeated to maintain a 1pps output pulse to AIF. PTP Sync Returns Timing is far off Time Sync Achieved Generate 1pps In Lock Time Sync Achieved Sync Pulse Generated Sync Output Re-sync
IEEE 1588 DPLL SW In-Lock Once the 1pps has been generated the AIF is synchronized to absolute time with the master time server. Software keeps going back to the Sync Output state to load the CPTS compare register with the next value for the 1pps. Fast Resync Required Initial Lock Holdover PTP Sync Lost The DPLL software needs to keep tracking the master clock to keep the local frequency in lock with the master frequency. PTP Sync Returns Timing is OK PTP Sync Returns Timing is far off Time Sync Achieved Generate 1pps In Lock Time Sync Achieved Sync Pulse Generated Sync Output Re-sync For this the DPLL software needs PTP sync pulses from the master time. The slave to master path time can be estimated with enough precision to lock the frequency so delay_req/delay_resp packets are needed less frequently. To estimate the arrival time the PTP clock sync app filters network impairments due to transit time variations of PTP Sync packets.
IEEE 1588 DPLL SW Holdover In the holdover state the voltage output to the DAC is held constant. Fast Resync Required The PTP capture events are monitored to see if the signal has returned. Initial Lock Holdover PTP Sync Lost PTP Sync Returns Timing is OK PTP Sync Returns Timing is far off Time Sync Achieved When PTP packets are captured DPLL software can determine how much drift has occurred in the local clock. If drift is too much re-sync state is entered. Else In-Lock state is entered. Generate 1pps In Lock Time Sync Achieved Sync Pulse Generated Sync Output Re-sync In some situations the drift might have caused the antenna to lose absolute time reference. Initial Lock is state is entered to re-calibrate CPTS timer and generate another sync pulse to the AIF.
IEEE 1588 DPLL SW Re-Sync The Re-sync state is entered because the radio frame timing has drifted outside of the specified timing window. Fast Resync Required Initial Lock Holdover PTP Sync Lost PTP Sync Returns Timing is OK PTP Sync Returns Timing is far off Time Sync Achieved Generate 1pps In Lock The DPLL algorithm slowly re-calibrates the local clock and locks the frequency to the master clock frequency. Time Sync Achieved Sync Pulse Generated Sync Output Re-sync
GPS Time Sync Time synchronization with GPS 1pps signal is almost identical to IEEE 1588 time synchronization. Ethernet PHY Packet Accelerator Clock Recovery Ethernet Packets Sync Packets SGMII The primary difference being that CPTS events to the GPS SW are generated by time stamping the 1pps signal through the TS_HW_PUSH events. HW Pulse 1 Sync Pulse 1-10 Hz Programmed Divider CPTS 1.3 HW Pulse 2 Ref CLK Active Antenna The GPS state machine in the clock sync application has the same 5 states as the 1588 state machine. PPS 1588 Stack DPLL Software SPI GPS Module UART GPS SW Clock Gen Chip VC- TCXO DAC
