Reactive Clocks with Variability-Tracking Jitter in ICCD 2015

Explore the research on reactive clocks with variability-tracking jitter presented at ICCD 2015. The study delves into the cost of variability margins, timing analysis, clock variability comparison between PLL and reactive clocks, and adaptive frequency utilization. Understand the benefits and implications of reactive clocks in terms of reducing margins and managing speed and energy efficiency.

• Reactive Clocks
• Variability Tracking
• Jitter
• ICCD 2015
• Timing Analysis

esau_30 Follow

Uploaded on Oct 11, 2024 | 0 Views

Download Presentation

Please find below an Image/Link to download the presentation.

The content on the website is provided AS IS for your information and personal use only. It may not be sold, licensed, or shared on other websites without obtaining consent from the author. Download presentation by click this link. If you encounter any issues during the download, it is possible that the publisher has removed the file from their server.

Presentation Transcript

1. Reactive Clocks with Variability-Tracking Jitter Jordi Cortadella, Luciano Lavagno, Pedro L pez, Marc Lupon, Alberto Moreno, Antoni Roca and Sachin S. Sapatnekar Universitat Polit cnica de Catalunya Politecnico di Torino University of Minnesota

2. The cost of variability margins frequency Reactive Clocks ICCD 2015 2

3. The cost of variability Impact: Goal: Reduce margins Speed Energy margins frequency Reactive Clocks ICCD 2015 3

4. Timing Flip Flops Flip Flops Combinational Logic PLL Reactive Clocks ICCD 2015 4

5. Timing: setup constraint Comb. Logic PVTA variability Two competing paths: Launching path Capturing path Launching path < Capturing path + Period 1 2 1 1 2 2 No variability (or very little) + PLL Margins Reactive Clocks ICCD 2015 5

6. Outline Reactive Clocks: how they work Understanding variability: Global/Local, Static/Dynamic Quantifying the benefits of Reactive Clocks Conclusions Reactive Clocks ICCD 2015 6

7. Reactive Clock Comb. Logic PVTA variability Correlated! Launching path < Capturing path + Period + PLL Margins Reactive Clocks ICCD 2015 7

8. Variability: PLL vs. Reactive Clock D time Q Q D launching path PLL period capturing path Reactive Clocks ICCD 2015 8

9. Variability: PLL vs. Reactive Clock D time Q Q D launching path PLL period capturing path D Q Q D clock-data compensation margin PLL period D Q Q D Reactive Clock Reactive Clocks ICCD 2015 9

10. PLL vs. Reactive Clock Adaptive frequency Reactive Clk (1.2V) 30% PLL (1.2V) Fixed frequency Reactive Clk (0.85V) Vdd = 1.2V 30% Reactive Clocks ICCD 2015 10

11. Outline Reactive Clocks: how they work Understanding variability: Global/Local, Static/Dynamic Quantifying the benefits of Reactive Clocks Conclusions Reactive Clocks ICCD 2015 11

12. Understanding variability WID (local) D2D (global) Source: H. Masuda et al. (ICICC 2005) Reactive Clocks ICCD 2015 12

13. Understanding variability Static Dynamic Slow (ms) Dynamic Fast (ns) Global (corners) PV VTA V Local (OCV) PV VTA V Margins Worst-case sign-off Binning Reactive Clocks Static Variability (PV) Dynamic Variability (VTA) Static Variability (PV) Dynamic Variability (VTA) Static Variability (PV) Dynamic Variability (VTA) Global X X X Local X X X X Only margins for local dynamic variability Margins removed after binning Reactive Clocks ICCD 2015 13

14. Outline Reactive Clocks: how they work Understanding variability: Global/Local, Static/Dynamic Quantifying the benefits of Reactive Clocks Conclusions Reactive Clocks ICCD 2015 14

15. Reactive Clock Gain: 40% less Energy or 1.6x speed-up Pain: Negligible Clock domain Risk: Zero Original circuit not modified Negligible area Post-tapeout calibration (by SW) Conventional timing (PrimeTime) Enable Reactive Clock PLL Reactive Clocks ICCD 2015 15

16. PLL vs. Reactive Clocks SPICE models (65nm) DUT 75oC 25oC 125oC temperature PLL Rclk Reactive Clocks ICCD 2015 16

17. PLL vs. Reactive Clocks SPICE models (65nm) DUT 75oC 25oC 125oC temperature PLL Rclk Slow 125oC Timing sign-off Reactive Clocks ICCD 2015 17

18. PLL vs. Reactive Clocks SPICE models (65nm) DUT 75oC 25oC 125oC temperature PLL Rclk Typical 125oC Slow 125oC Timing sign-off Ideal binning Reactive Clocks ICCD 2015 18

19. PLL vs. Reactive Clocks SPICE models (65nm) DUT 75oC 25oC 125oC temperature PLL Rclk Typical 125oC Slow 75oC Slow 125oC Timing sign-off Reactive Clocks ICCD 2015 19

20. PLL vs. Reactive Clocks SPICE models (65nm) DUT 75oC 25oC 125oC temperature PLL PLL Rclk Rclk Typical 125oC Slow 75oC Typical 75oC Slow 125oC Timing sign-off Reactive Clocks ICCD 2015 20

21. PLL vs. Reactive Clocks SPICE models (65nm) DUT 75oC 25oC 125oC temperature PLL PLL Rclk Rclk and great benefits for Typical 125oC hostile environmental conditions (> 2x) Slow 75oC Typical 75oC Slow 125oC 1.2x Timing sign-off 1.6x Reactive Clocks ICCD 2015 21

22. PLL vs. Reactive Clocks SPICE models (65nm) DUT 75oC 25oC 125oC temperature PLL PLL Rclk Rclk sign-off -20% (1.07V) -42% (0.91V) Energy reduction (@iso-performance) Reactive Clocks ICCD 2015 22

23. Synthesis of the Ring oscillator Delay PLL period OCV Library Corners Programmable by SW Reactive Clocks ICCD 2015 23

24. Conclusions Moore s law is (economically) over. It s time to exploit what is left in established nodes. What s left? Margins for dynamic variability. Reactive Clocks: a zero-risk technology to boost performance (1.6x speedup) or reduce energy (40%) Thank you! Reactive Clocks ICCD 2015 24